Enhancement of Current Drivability of Nanograting Polycrystalline Silicon Thin-Film Transistors

Kuroki, Shinichiro; Zhu, Xiaoli; Kotani, Kazuhiko; Ito, Takashi

doi:10.1143/jjap.49.04dj11

Cited by 3 publications

(1 citation statement)

References 37 publications

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“…Poly-Si TFTs will be applied to integrated circuits with multiple tasks such as photovoltaic power generation, CMOS logic and sensor (50). Poly-Si TFT will be a key element for large area devices to be applied medical industry field (58).…”

Section: Future Tft Technologiesmentioning

confidence: 99%

(Invited) Polycrystalline Silicon Thin Film Transistors

Sameshima¹

2010

ECS Trans.

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Technologies of polycrystalline silicon thin film transistors (polySi TFTs) are reviewed. Many important technologies have been developed in recent twenty years for establishing low processing temperature fabrication of poly-Si TFTs in order to use glass or plastic substrates. There have been rapid thermal annealing methods for formation of poly-Si films, defect passivation of polySi grain boundaries, and SiO 2 formation. Structural and electrical properties of poly-Si films are also discussed. Characterization and evaluation methods are also reviewed. They are important for developing poly-Si TFTs processing. We discuss capability of TFT performance and possibility of application to electronic devices in future.

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Section: Future Tft Technologiesmentioning

confidence: 99%

(Invited) Polycrystalline Silicon Thin Film Transistors

Sameshima¹

2010

ECS Trans.

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Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

Hara

Kamo

Satô

2014

IEICE Trans. Electron.

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SUMMARY Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550 • C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5 µm and TG and BG SiO 2 thicknesses of 50 and 100 nm, respectively, exhibited a subthreshold swing of 120 mV/dec and a threshold voltage (V th ) of −0.5 V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor (γ = ∆V th /∆V BG ) of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g m also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.

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Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

Ohsawa¹,

Sasaki²,

Hara³

2016

Jpn. J. Appl. Phys.

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Self-aligned four-terminal n-channel (n-ch) and p-channel (p-ch) planar embedded metal double-gate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature of 550 °C. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are used as the drive and control gates or vice versa. The BG was embedded in a glass substrate, and a poly-Si channel with large lateral grains was fabricated by continuous-wave laser lateral crystallization. The threshold voltage modulation factors under various control gate voltages (γ = ΔV th/ΔV CG) were nearly equal to the theoretical predictions in both the n- and p-ch TFTs. By exploiting this high controllability, an enhancement depletion (ED) inverter was fabricated, and successful operation at 2.0 V was confirmed.

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Enhancement of Current Drivability of Nanograting Polycrystalline Silicon Thin-Film Transistors

Cited by 3 publications

References 37 publications

(Invited) Polycrystalline Silicon Thin Film Transistors

(Invited) Polycrystalline Silicon Thin Film Transistors

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

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