Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

Abstract

Self-aligned four-terminal n-channel (n-ch) and p-channel (p-ch) planar embedded metal double-gate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature of 550 °C. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are used as the drive and control gates or vice versa. The BG was embedded in a glass substrate, and a poly-Si channel with large lateral grains was fabricated by continuous-wave laser lateral crystallization. The threshold voltage modulation factors under various control gate voltages (γ = ΔV th/ΔV CG) were nearly equal to the theoretical predictions in both the n- and p-ch TFTs. By exploiting this high controllability, an enhancement depletion (ED) inverter was fabricated, and successful operation at 2.0 V was confirmed.

Performance of four-terminal low-temperature polycrystalline-silicon thin-film transistors and their application in CMOS inverters on glass substrates

“…The numbers in parentheses are the predicted values of γ, according to the theory proposed by Masahara et al 53,54) Figure 3(b) shows the variation in V th with respect to V CG for p-ch 4T E-MeDG LT poly-Si TFTs, as well as V th of the p-ch TFT in a CMOS inverter, which is plotted with large open circles. 45,46,51) We observed a "bending point" for the variation in γ with respect to V CG for the n-ch TFTs, which were fabricated with their own processes on different glass substrates. V th of the n-ch TFT in CMOS was on their extrapolated line.…”

“…Figures 3(a) and 3(b) show V th for n-and p-ch 4T E-MeDG CLC LT poly-Si TFTs, respectively, which are fabricated on different substrates with their own processes. 45,46) The original data of the black and red points in this figure are taken from Refs. 45 and 46.…”

“…41,42) To control V th , we fabricated 4T planar embedded metal double-gate (E-MeDG) LT TFTs using a high-quality CLC poly-Si film. [43][44][45][46] These devices comprised a top metal gate (TG) and a bottom metal gate (BG), where the BG was embedded in a glass substrate using chemical mechanical polishing (CMP). 47) In addition, the TG was fabricated via a self-alignment process using back-side exposure with the BG as a photomask.…”

Bottom gate single crystal Si thin-film transistors fabricated by all sputtering processes

“…Although LTPS top-gate TFTs (TG-TFTs) have been widely applied for driving OLEDs, BG TFTs are also in high demand because of their compatibility with fabrication process of a-Si BG-TFTs. Several groups have proposed LTPS BG-TFTs in which a-Si precursor films are crystallized by either excimer laser crystallization (ELC), [6][7][8][9] or cw laser crystallization (CLC), 10,11,12) However, the uniformity of TFTs is also an important issue for high-definition displays because the variation of grain numbers in the channel region causes characteristic deviation of TFTs. Single-crystal Si (c-Si) TFTs provide the ultimate solution to this challenge.…”

A Comparative Study of E-Beam Deposited Gate Dielectrics on Channel Width-Dependent Performance and Reliability of a-IGZO Thin-Film Transistors

“…In addition, a -IGZO TFTs can be fabricated on silicon wafer, glass, and also flexible organic substrates. The prevailing amorphous silicon ( a -Si:H) exhibits a low carrier mobility (0.5–1 cm 2 /V·s), while the polycrystalline silicon (poly-Si) requires high-temperature fabrication processes (>500 °C) [6,7]. However, recent studies have found that the performance of TFTs is very much dependent upon the gate dielectric material and its deposition method [8].…”