Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

Abstract

SUMMARY Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550 • C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5 µm and TG and BG SiO 2 thicknesses of 50 and 100 nm, respectively, exhibited a subthreshold swing of 120 mV/dec and a threshold voltage (V th ) of −0.5 V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor (γ = ∆V th /∆V BG ) of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g m also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.

Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

“…27,28) Recently, we fabricated four-terminal (4T) self-aligned planar E-MeDG n-channel (n-ch) CLC LT poly-Si TFTs by modulating the process features of self-aligned planar E-MeDG CLC LT poly-Si TFTs. 29) This device includes a metal top gate (TG) and metal bottom gate (BG), which are used as the drive and control gates or vice versa. A poly-Si channel with large lateral grains was fabricated using CLC, and the BG was embedded in the glass substrate.…”

Low-temperature metal double-gate junctionless p-channel polycrystalline-germanium thin-film transistors with high-k gate dielectric on glass substrate

“…After the formation of a contact hole to connect the top and bottom metal gates, the top Mo metal was deposited by sputtering. The top gate metal was designed using a mask alignment process, but not the self-aligned process developed by one of the authors (A.H.) for poly-Si TFTs [2][3][4][5] . After the interlayer formation, electrodes were deposited by sputtering.…”

Performance of four-terminal low-temperature polycrystalline-silicon thin-film transistors and their application in CMOS inverters on glass substrates

“…41,42) To control V th , we fabricated 4T planar embedded metal double-gate (E-MeDG) LT TFTs using a high-quality CLC poly-Si film. [43][44][45][46] These devices comprised a top metal gate (TG) and a bottom metal gate (BG), where the BG was embedded in a glass substrate using chemical mechanical polishing (CMP). 47) In addition, the TG was fabricated via a self-alignment process using back-side exposure with the BG as a photomask.…”