Low-temperature metal double-gate junctionless p-channel polycrystalline-germanium thin-film transistors with high-k gate dielectric on glass substrate

Nishimura, Yuya; Nibe, Shota; Hara, Akito

doi:10.1109/am-fpd.2015.7173250

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…Multi-gate MOS device structures like FinFETs, which use multiple gate electrodes and an ultrathin body, have been developed to address these challenges, showing an excellent device performance at Micromachines 2024, 15, 726 2 of 26 scaled parameters. The use of metal gates has become attractive due to their chemical stability with high-κ gate dielectrics and the ability to maintain higher threshold voltages while acquiring high gate stack stability [9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

Ülkü,

Uçar,

Serin

et al. 2024

Micromachines

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Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell–Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10−15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10−11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

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Section: Introductionmentioning

confidence: 99%

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

Ülkü,

Uçar,

Serin

et al. 2024

Micromachines

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show abstract

“…In our previous research, we reported a planar metal double-gate (MeDG) JL p-ch LT solid-phase crystallization (SPC) poly-Ge TFT on a glass substrate with a 25-nm-thick poly-Ge film. 36) The TFT had an on=off ratio of 7, which is a relatively small value. We also developed a self-aligned planar MeDG JL p-ch LT SPC poly-Ge TFT on a glass substrate with a 20-nm-thick poly-Ge film.…”

Section: Introductionmentioning

confidence: 99%

Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

Hara

Nishimura

Ohsawa

2016

Jpn. J. Appl. Phys.

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Low-temperature (LT) polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) are viable contenders for use in the backplanes of flat-panel displays and in systems-on-glass because of their superior electrical properties compared with silicon and oxide semiconductors. However, LT poly-Ge shows strong p-type characteristics. Therefore, it is not easy to reduce the leakage current using a single-gate structure such as a top-gate or bottom-gate structure. In this study, self-aligned planar metal double-gate p-channel junctionless LT poly-Ge TFTs are fabricated on a glass substrate using a 15-nm-thick solid-phase crystallized poly-Ge film and aluminum-induced lateral metallization source–drain regions (Al-LM-SD). A nominal field-effect mobility of 19 cm2 V−1 s−1 and an on/off ratio of 2 × 103 were obtained by optimizing the Al-LM-SD on a glass substrate through a simple, inexpensive LT process.

show abstract

Low-temperature metal double-gate junctionless p-channel polycrystalline-germanium thin-film transistors with high-k gate dielectric on glass substrate

Cited by 2 publications

References 5 publications

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

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