Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

Hara, Akito; Nishimura, Yuya; Ohsawa, Hiroki

doi:10.7567/jjap.56.03bb01

Cited by 25 publications

(31 citation statements)

References 42 publications

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“…Finally, annealing at 300 °C was performed to facilitate the formation of metal-SD by atomic exchange between Al and Ge, which is named as aluminum-induced lateral metallization SD (Al-LM-SD). This technique was first reported by A. H., and we used it to form low parasitic resistance metallic SD [18]. Figure 2 shows the top-view photograph of the fabricated TFT with a gate length of 20 μm.…”

Section: Experimental Methodsmentioning

confidence: 99%

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate

Nishiguchi

Miyazaki

Utsumi

et al. 2018

Symp Digest of Tech Papers

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In this study, we fabricated p‐channel (p‐ch) poly‐Ge1‐x Snx thin‐film transistors (TFTs) on glass substrates using three key technologies. They are the self‐aligned double‐gate (DG) structure, metal‐induced crystallization using copper (Cu‐MIC), and aluminum‐induced lateral metallization source drain (Al‐LM‐SD). An amorphous Ge1‐x Snx film, which was prepared using a sputtering target with x=0.02 and 0.07, was crystallized by Cu MIC at 500 °C, and it was observed that Cu‐MIC enables us to fabricate a high‐quality poly‐Ge1‐x Snx thin film. The self‐aligned DG Cu‐MIC p‐ch poly‐Ge1‐x Snx TFTs, with x=0.02 and 0.07, achieved mobility of 18 and 25 cm2/Vs, respectively. Our proposed p‐ch TFT will facilitate fabrication of hybrid CMOS with n‐ch indium‐gallium‐zinc‐oxide TFT.

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Section: Experimental Methodsmentioning

confidence: 99%

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate

Nishiguchi

Miyazaki

Utsumi

et al. 2018

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“…TFT performance Figure 6 shows the fabricated TFTs, which were annealed for 60 min at 300 °C, the final annealing to form Al-LM-SD. Our previous study demonstrated that the gray region in the SD comprises metallic Al, which is grown by a lateral atomic exchange process between the electrode Al and poly-Ge film [5]. This leads to low parasitic resistance of the SD region and high on-current by a simple and inexpensive process at a low temperature of 300 °C.…”

Section: P-228 / H Utsumimentioning

confidence: 99%

“…In our previous research, we reported a self-aligned planar metal double-gate (MeDG) JL p-ch LT solid-phase crystallization (SPC) poly-Ge TFT on a glass substrate, where in a 15-nm-thick SPC poly-Ge film and aluminum (Al) induced lateral metallization (LM) source-drain (Al-LM-SD) were used to reduce the offcurrent and SD resistance [5]. A self-alignment process was used to align the top and bottom metal gates, in which the bottom metal gate was used as a photomask.…”

Section: Introductionmentioning

confidence: 99%

“…A self-alignment process was used to align the top and bottom metal gates, in which the bottom metal gate was used as a photomask. The TFTs had an on/off ratio of 2 × 10 3 and a mobility of 19 cm 2 /Vs [5]. However, these TFTs were fabricated at a temperature of 500 °C, while using the SPC process.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we demonstrate a novel method to fabricate poly-Ge TFTs at a temperature of 300 °C on a glass substrate. We used three key technologies: a self-aligned planar MeDG structure to reduce off-current [5]; metal induced crystallization (MIC) using copper (Cu) (Cu-MIC) to fabricate poly-Ge film at 300 °C [6][7][8];…”

Section: Introductionmentioning

confidence: 99%

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P‐228: Late‐News Poster: Self‐Aligned Planar Metal Double‐Gate Cu‐MIC Poly‐Ge TFTs Fabricated at 300°C on a Glass Substrate

Utsumi

Sasaki

Sekiguchi

et al. 2017

Symp Digest of Tech Papers

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Self-aligned planar metal double-gate p-channel polycrystallinegermanium thin-film transistors were fabricated at 300 °C on a glass substrate by copper metal induced crystallization and lateral metallization of source-drain using aluminum electrodes. A nominal mobility of 25 cm 2 /Vs was obtained owing to the high hole mobility of germanium, and an on/off ratio of 30 was achieved by the double-gate structure. Our proposal is expected to be a novel method for fabricating high-performance TFTs on plastic substrates.

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A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

Böckle

Sistani

Lipovec

et al. 2021

Adv Materials Technologies

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A popular approach to overcome this limitation is the course-grain reconfiguration, i.e. the signal routing to predefined logic blocks as practiced in field programmable gate arrays (FPGA). [1] This approach nevertheless leads to a high latency in data transfer and substantial chip area consumption since few active regions are not utilized at once. Distinctly, the ansatz of reconfiguration of elementary function blocks, i.e. the fine-grain reconfiguration, gives rise to a paradigm change where devices and circuits are actively redesigned after manufacturing and noteworthy even at runtime. Thereto, combinational circuits have shown benefits in area and power consumption by reconfiguration of complete logic blocks. [2] The building blocks for such circuits are RFETs, capable of merging the electrical properties of unipolar p-and n-type FETs into a single type of device with identical technology, geometry and composition. [3][4][5] Notably, RFETs do not require doping in contrast to classical FETs. Thereto, a device layout with independent gates is used to induce an additional energy barrier to the channel that blocks the undesired charge carrier type and therefore favors p-or n-type operation respectively. Consequently, reducing the technological fabrication complexity, they enable dynamic programming of circuits at the device level. [3,5] Prominent applications of such RFET devices are currently arising in the area of hardware security [6] and in highly integrated combinational and sequential logic. [5,7] Different channel materials have been employed to realize RFETs. With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes. In this sense, Ge and SiGe have been identified as promising channel materials due to their reduced bandgap compared to the one of Si. Since the highest fraction of transport relevant for device and circuit performance is dictated by quantum mechanical tunneling of charge carriers [12] the use of Ge and Si x Ge 1-x channels Conventional field-effect transistor (FET) concepts are limited to static electrical functions and demand extraordinarily steep and reproducible doping concentration gradients. Reaching the physical limits of scaling, doping-free reconfigurable field-effect transistors (RFETs) capable of dynamically altering the device operation between p-or n-type, even during runtime, are emerging device concepts. In this respect, Ge has been identified as a promising channel material to enable reduction of power consumption and switching delay of RFETs. Nevertheless, its us...

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Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

Cited by 25 publications

References 42 publications

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate

P‐228: Late‐News Poster: Self‐Aligned Planar Metal Double‐Gate Cu‐MIC Poly‐Ge TFTs Fabricated at 300°C on a Glass Substrate

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

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Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

Cited by 25 publications

References 42 publications

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge1‐x Snx Thin‐Film Transistors on a Glass Substrate

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge1‐x Snx Thin‐Film Transistors on a Glass Substrate

P‐228: Late‐News Poster: Self‐Aligned Planar Metal Double‐Gate Cu‐MIC Poly‐Ge TFTs Fabricated at 300°C on a Glass Substrate

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

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Product

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P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate

P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge_1‐x Sn_x Thin‐Film Transistors on a Glass Substrate