Electronic properties of InAs-based metal-insulator-semiconductor (MIS) structures

Kuryshev, G. L.; Kovchavtsev, A. P.; Valisheva, N. A.

doi:10.1134/1.1403571

Cited by 17 publications

(10 citation statements)

References 13 publications

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“…1͑b͒. Figure 2͑a͒ shows the multifrequency C-V curves measured on the MOS capacitors annealed at 360°C for 30 s. The minimum capacitance was observed at ϳ−1 V. This is a smaller flatband voltage shift than previous reported values, [3][4][5] suggesting a much less bulk and interface trap densities. The MOS capacitor shows evidence of hole accumulation for negative biases and inversion for positive biases.…”

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confidence: 73%

“…2 However, as is the case with most III-V semiconductors, the primary obstacle for the development of InAs MOSFET is the lack of a high-quality insulatorsemiconductor interface. Previous efforts to develop InAs metal-oxide-semiconductor ͑MOS͒ structures with anodic oxide 3,4 and deposited SiO 2 ͑Ref. 5͒ resulted in big negative shifts of flatband voltage and large hysteresis, indicating high interface-state and bulk oxide charge densities.…”

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confidence: 99%

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Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Harmon

Hyland

et al. 2008

Applied Physics Letters

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InAs is very attractive as a channel material for high-speed metal-oxide-semiconductor ͑MOS͒ field-effect transistors due to its very high electron mobility and saturation velocity. We investigated the processing conditions and the interface properties of an InAs metal-oxide-semiconductor structure with Al 2 O 3 dielectric deposited by atomic-layer deposition. The MOS capacitor I-V and C-V characteristics were studied and discussed. Simple field-effect transistors fabricated on an InAs bulk material without source/drain implantation were measured and analyzed.

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confidence: 73%

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confidence: 99%

Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Harmon

Hyland

et al. 2008

Applied Physics Letters

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“…It is highly likely that the disorder of the interface was reduced by forming a sufficiently thick native oxide layer. Actually, using the native oxide layer as an interlayer is also an efficient means of forming excellent insulator–semiconductor interfaces for other semiconductors . To achieve a low D it , however, a low‐damage process is conventionally used, that is, an electrochemical process .…”

Section: Resultsmentioning

confidence: 99%

“…Actually, using the native oxide layer as an interlayer is also an efficient means of forming excellent insulator–semiconductor interfaces for other semiconductors . To achieve a low D it , however, a low‐damage process is conventionally used, that is, an electrochemical process . The recently reported plasma oxidation of a GaAs surface to form a good insulator–semiconductor interface is a noteworthy means of increasing the flexibility of the interface formation process.…”

Section: Resultsmentioning

confidence: 99%

Reduction of interface state density at SiO₂/InAlN interface by inserting ultrathin Al₂O₃ and plasma oxide interlayers

Akazawa

seino

2017

Physica Status Solidi (b)

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SiO2/InAlN interfaces formed by plasma‐enhanced chemical vapor deposition were investigated. X‐ray photoelectron spectroscopy showed that the direct deposition of SiO2 onto an InAlN surface led to the oxidation of the InAlN surface. The interface state density, Dit, was on the order of 1012 cm−2 eV−1 (5 × 1012 cm−2 eV−1 at 0.3 eV from the conduction band edge, Ec), which indicated the possibility of improving the interface properties. Reduction of the interface state density was attempted using an Al2O3 interlayer and a plasma oxide interlayer. The insertion of a 2‐nm‐thick Al2O3 interlayer to prevent surface oxidation by plasma reduced Dit slightly. A marked reduction in Dit to less than 1011 cm−2 eV−1 deeper than 0.3 eV from Ec, however, was achieved by the intentional formation of a 1‐nm‐thick plasma oxide layer, formed by N2O plasma oxidation, as an interlayer between SiO2 and InAlN.

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“…2,3 Indium arsenide (InAs) has a high electron mobility of $30,000 cm 2 /V s and a saturation velocity of 8 Â 10 7 cm/s 4,5 and is an excellent channel material. In early studies, InAs metal-oxide-semiconductor (MOS) capacitors that were made by anodic oxide 6 and pyrolytically deposited SiO 2 7 yielded negative flat-band shifts and large hysteresis, indicating high densities of interface states and bulk fixed charges. Recently, W. Prost 8 and Q.-T. Do 9 demonstrated InAs nanowire MOSFETs using SiN x gate dielectrics that were deposited by PECVD.…”

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confidence: 99%

Low Output-Conductance InAs-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with SiO2 Gate Dielectrics

Fan

Lin

2011

Electrochem. Solid-State Lett.

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This study reports the development of InAs-channel MOSFETs using PECVD-deposited SiO 2 gate dielectrics. Arsenic capping and desorption are applied to as-grown wafers to prevent the formation of native oxides before the gate dielectrics are then deposited. We believe that increased hole confinement in a layer structure effectively suppresses the impact ionization effect, and an output conductance as 18 mS/mm at a drain bias of 2 V is demonstrated. A 2 m-gate-length device exhibits dc performances of I DSS ¼ 154 mA/mm and g m ¼ 189 mS/mm, and rf performances of f T ¼ 14.5 GHz and f MAX ¼ 24 GHz. The InAs-channel MOS-FET has potential for application in high frequency circuit devices.In VLSI logic circuits, Si CMOS technology is expected to reach the scaling limit beyond 22-nm technology nodes. III-V compound materials are promising alternative channel materials to Si owing to their high-electron mobility. 1 However, a primary problem associated with the III-V MOSFETs is a lack of high-quality insulator-semiconductor interfaces. Related investigations have addressed the development of Ga 2 O 3 , Gd 2 O 3 , Al 2 O 3 , SiN x , HfO 2 and other gate dielectrics on III-V or Si channel materials. 2,3 Indium arsenide (InAs) has a high electron mobility of $30,000 cm 2 /V s and a saturation velocity of 8 Â 10 7 cm/s 4,5 and is an excellent channel material. In early studies, InAs metal-oxide-semiconductor (MOS) capacitors that were made by anodic oxide 6 and pyrolytically deposited SiO 2 7 yielded negative flat-band shifts and large hysteresis, indicating high densities of interface states and bulk fixed charges. Recently, W. Prost 8 and Q.-T. Do 9 demonstrated InAs nanowire MOSFETs using SiN x gate dielectrics that were deposited by PECVD. Enhanced dc but degraded rf performance were observed. This degradation is again primarily due to the charge trapping at dielectric/semiconductor interface. N. Li 10 developed MOS capacitors and FETs on bulk InAs materials using the Al 2 O 3 gate dielectrics of atomic layer deposition (ALD). The FETs exhibited incomplete pinch-off while low leakage was demonstrated in the MOS capacitors.Conventional InAs-channel heterojunction field-effect transistors (HFETs) suffer from high kink currents owing to a small InAs bandgap of 0.36 eV along with a type-II band lineup at the InAs-AlSb interfaces 11 Impact-ionized holes, which cannot be confined to the channel, either move to gate electrodes, increasing onstate leakage or accumulate in the buffer, inducing high kink currents (high output conductance). The high kink currents limit the feasible drain bias below 0.5 V and further applications in circuit design.To improve the incomplete pinch-off in the MOSFET and the poor hole confinement in the HFET, we propose a layer structure for developing the InAs-channel MOSFETs, which consists of high-resistivity Al(Ga)Sb layers in the buffer to avoid potential leakage paths through the conductive InAs buffer layer and a n-type doping sheet in the buffer to form a hole energy barrier. Epitaxial growth, de...

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Electronic properties of InAs-based metal-insulator-semiconductor (MIS) structures

Cited by 17 publications

References 13 publications

Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Reduction of interface state density at SiO₂/InAlN interface by inserting ultrathin Al₂O₃ and plasma oxide interlayers

Low Output-Conductance InAs-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with SiO2 Gate Dielectrics

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Electronic properties of InAs-based metal-insulator-semiconductor (MIS) structures

Cited by 17 publications

References 13 publications

Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric

Reduction of interface state density at SiO2/InAlN interface by inserting ultrathin Al2O3 and plasma oxide interlayers

Low Output-Conductance InAs-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with SiO2 Gate Dielectrics

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Reduction of interface state density at SiO₂/InAlN interface by inserting ultrathin Al₂O₃ and plasma oxide interlayers