Electronic Properties of <font>GaN</font> (0001) – Dielectric Interfaces

Cook, T. E.; Fulton, C. C.; Mecouch, W. J.; Davis, R.F.; Lucovsky, G.; Nemanich, R. J.

doi:10.1142/9789812562364_0007

Cited by 2 publications

(3 citation statements)

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“…Of course, different oxide growth condition might lead to different BO lign-up which essentially influences the confinement of the carrier electrons. 27,56 It is worthwhile to point out that there are two ways to work out the band offsets between two semiconductors/insulators, i.e., LDOS and average potentials line-up methods. 57,58 In principle, these two methods provide the same outcomes with minor differences.…”

Section: Band Offsetsmentioning

confidence: 99%

“…In addition, the experimental data on Fermi level pinning on cubic GaN surface can motivate this study. 26 27 The density of interface states, resulting in Fermi level pinning, is another important factor impacting the interface quality. 28, 29 Guo et al 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 4 claimed the improvement to the GaAs/Al2O3 interface quality by nitridation the GaAs surface prior to the HfO2 deposition using first principles calculation.…”

Section: Introductionmentioning

confidence: 99%

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GaN as an Interfacial Passivation Layer: Tuning Band Offset and Removing Fermi Level Pinning for III–V MOS Devices

Zhang

Cao

Wang

et al. 2015

ACS Appl. Mater. Interfaces

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The use of an interfacial passivation layer is one important strategy for achieving a high quality interface between high-k and III-V materials integrated into high-mobility metal-oxide-semiconductor field-effect transistor (MOSFET) devices. Here, we propose gallium nitride (GaN) as the interfacial layer between III-V materials and hafnium oxide (HfO2). Utilizing first-principles calculations, we explore the structural and electronic properties of the GaN/HfO2 interface with respect to the interfacial oxygen contents. In the O-rich condition, an O8 interface (eight oxygen atoms at the interface, corresponding to 100% oxygen concentration) displays the most stability. By reducing the interfacial O concentration from 100 to 25%, we find that the interface formation energy increases; when sublayer oxygen vacancies exist, the interface becomes even less stable compared with O8. The band offset is also observed to be highly dependent on the interfacial oxygen concentration. Further analysis of the electronic structure shows that no interface states are present at the O8 interface. These findings indicate that the O8 interface serves as a promising candidate for high quality III-V MOS devices. Moreover, interfacial states are present when such interfacial oxygen is partially removed. The interface states, leading to Fermi level pinning, originate from unsaturated interfacial Ga atoms.

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Section: Band Offsetsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

GaN as an Interfacial Passivation Layer: Tuning Band Offset and Removing Fermi Level Pinning for III–V MOS Devices

Zhang

Cao

Wang

et al. 2015

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

show abstract

“…) and s e q pol SiO 2 are set to constant values of 1.6 V and 0.5878 V nm −1 , assuming: 3.4−0.3=6.4 eV [25,35] for a semi-isolating GaN buffer; -ψ s,max =maximum potential drop in semi-isolating GaN=E C −E F ≈3.4−0.3=3.1 V; -σ pol =1.2685×10 13 cm −2 corresponding to 23% Al concentration in the barrier for the AlGaN/GaN system [36].…”

Section: Threshold Voltage Trendsmentioning

confidence: 99%

ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications

Ramanan

Lee

Misra

2015

Semicond. Sci. Technol.

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Dielectrics by atomic layer deposition (ALD) are sought after for fabricating AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors (MOS-HFETs) for power applications. The ideal gate dielectric is required to suppress gate leakage and minimize threshold voltage (V T ) instability by hosting minimal interface traps. Additionally, with the need for an enhancement mode device, it is preferable if it minimizes V T shift in the negative direction. For the first time, we compare popular ALD dielectrics like SiO 2 , Al 2 O 3 , HfO 2 and HfAlO with identical electrical thickness on AlGaN/GaN, thereby ensuring identical electrostatic conditions across different dielectrics. High-k ALD dielectrics (HfAlO, HfO 2 and Al 2 O 3 ) are found to suppress gate leakage but host a high density of interface traps with AlGaN, thereby resulting in significant V T instability. ALD SiO 2 gate dielectric, annealed in N 2 above 600 °C, is a promising gate dielectric candidate which provides the most stable and least negative shift in V T while also substantially suppressing gate leakage below that of an HFET.

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Electronic Properties of GaN (0001) – Dielectric Interfaces

Cited by 2 publications

References 0 publications

GaN as an Interfacial Passivation Layer: Tuning Band Offset and Removing Fermi Level Pinning for III–V MOS Devices

GaN as an Interfacial Passivation Layer: Tuning Band Offset and Removing Fermi Level Pinning for III–V MOS Devices

ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications

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