Reliability of dielectrics is a critical concern inGaN metal-oxide-semiconductor-heterojunction-field-effect transistor (MOS-HFET) devices for use in high-voltage power and RF applications. Accurate characterization of interface traps is essential toward developing an understanding of the reliability issues associated with this system and to evaluate the effectiveness of different dielectrics proposed for use in the gate-stack or the passivation of the access regions. Using small-signal equivalent circuit models and TCAD simulations, it is found that conductance and capacitance methods for trap density estimation potentially have severely constrained detection limits and can probe only shallow traps. In contrast, a pulsed-IV method, used along with UV irradiation, can accurately detect a wide range of trap densities over the entire wide bandgap. The effectiveness of this method is also experimentally demonstrated using an AlGaN/GaN MOS-HFET device with HfAlO gate dielectric.

In order to minimize ac-dc dispersion, reduce gate leakage and maximize ac transconductance, there is a critical need to identify optimal interfaces, low-k passivation dielectrics and high-k gate dielectrics. In this paper, an investigation of different atomic layer deposited (ALD) passivation dielectrics on AlGaN/GaN-based hetero-junction field effect transistors (HFETs) was performed. Angle-resolved x-ray photoelectron spectroscopy revealed that HCl/HF and NH 4 OH cleans resulted in a reduction of native oxide and carbon levels at the GaN surface. The role of high temperature anneals, following the ALD, on the effectiveness of passivation was also explored. Gate-lag measurements on HFETs passivated with a thin ALD high-k Al 2 O 3 or HfAlO layer capped with a thick plasma enhanced chemical vapor deposited (PECVD) low-k SiO 2 layer, annealed at 600-700 • C, were found to be as good as or even better than those with conventional PECVD silicon nitride passivation. Further, it was observed that different passivation dielectric stacks required different anneal temperatures for improved gate-lag behavior compared to the as-deposited case.

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Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps with a variety of ALD dielectrics. High-k dielectrics (HfO2, HfAlO, and Al2O3) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO2 shows the lowest interface trap density (<2 × 1012 cm−2) after annealing above 600 °C in N2 for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.

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