Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique

Åberg, Ingvar; Olubuyide, O.O.; Chleirigh, C.N.; Lauer, Isaac; Antoniadis, D.A.; Li, J.; Hull, R.; Hoyt, Judy L.

doi:10.1109/vlsit.2004.1345388

Cited by 19 publications

(14 citation statements)

References 2 publications

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“…Long channel hole transport under biaxial tensile strain with 12-nm-thick Si film remains advantageous with a +4% μ h -enhancement. This result is in good agreement with previous experimental data in UTB MOSFETs [9] and can be explained as follows; the biaxial tensile strain removes the degeneracy of the valence band and modifies the band structure in a manner that reduces the effective hole masse. For thinner silicon films the degeneracy of the light and heavy holes is already lifted due to the strong confinement effects, hence the mobility gain is reduced [10].…”

Section: Resultssupporting

confidence: 91%

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud¹,

Laviéville²,

Tabone³

et al. 2014

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

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High-performance strainedSilicon-OnInsulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I ON current of 1410 μA/μm (when I OFF = 70 nA/μm) at V DD =0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS SAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I ON improvement up to +40% at short gate lengths. More generally, size-and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.

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Section: Resultssupporting

confidence: 91%

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud¹,

Laviéville²,

Tabone³

et al. 2014

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

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“…The two most promising approaches in integrating such novel channel materials within a novel architecture are the strained-Si-on-insulator (SSOI) (Langdo et al, 2002;Aberg et al, 2004) and SiGe-on-insulator (SGOI) (Huang et al, 2001) or Ge-on-insulator (GOI) (Huang et al, 2003) approaches. In this section, we review some of the approaches that have successfully implemented high-carrier-mobility channel materials within the single-gate UTB/FDSOI architecture.…”

Section: Novel Materials-based Single-gate Utb/fdsoi Mosfetmentioning

confidence: 99%

Silicon MOSFETs for ULSI: Scaling CMOS to Nanoscale

Dey

Banerjee²

2011

Comprehensive Semiconductor Science and Technology

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“…Starting substrates were 6-in 30% strained-Si-directly-oninsulator wafers (strained to Si 0.7 Ge 0.3 virtual substrates), fabricated utilizing a bond-and-etch-back technique [11]. These substrates were biaxially strained to 2.16-GPa tension, as confirmed by UV micro-Raman spectroscopy [10].…”

Section: Device Design and Fabricationmentioning

confidence: 99%

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

Hashemi

Gomez

Hoyt

2009

IEEE Electron Device Lett.

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The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-MOSFETs are investigated for nanowire (NW) diameters down to 8 nm. Suspended strained-Si NWs with ∼2-GPa uniaxial tension were realized by nanopatterning-induced unilateral relaxation of ultrathin-body 30% strained-Si-directly-on-insulator substrates. Based on these NWs, GAA strained-Si n-MOSFETs were fabricated with a Si thickness of ∼8 nm and NW widths in the range of 50 nm down to 8 nm. The GAA strained-Si MOSFETs show excellent subthreshold swing and cutoff behavior, and approximately two times current drive and intrinsic transconductance enhancement compared to similar unstrained Si devices.

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Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique

Cited by 19 publications

References 2 publications

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Silicon MOSFETs for ULSI: Scaling CMOS to Nanoscale

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

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