Electrical–Thermal–Stress Coupled-Field Effect in SOI and Partial SOI Lateral Power Diode

Huang, Guang Yu; Tan, Cher Ming

doi:10.1109/tpel.2010.2090174

Cited by 4 publications

(1 citation statement)

References 33 publications

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“…The tool must be used to analyze the practice layout, to enter the electrical performance of the circuit and to calculate the impedance substrate matrix to analyze the substrate coupling. On this subject, some research programs have been published in recent years under electrical (Eo and Eisenstaedt, 1993;Savidis and Friedman, 2009), thermal (Lee, 2011;Schneider et al, 2008) or stress (Huang and Tan, 2011;Kong et al, 2011;Kwon et al, 2011;Ryu et al, 2012) analysis. The substrate extraction by BEM analysis has been proposed (Maffucci et al, 2004;de Magistris and de Tommasi, 2007;Weisshaar et al, 2002), but it is applied only to analyze coupling between contacts lying on the top surface of the substrate, not for 3D TSV structures.…”

Section: Introductionmentioning

confidence: 99%

Through silicon vias: from a physical point of view to a compact models initiation

Sun

Lorival

Calmon³

et al. 2014

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -The substrate coupling and loss in integrated circuits are analyzed. Then, the authors extract impedances between any numbers of embedded contacts. The paper aims to discuss these issues. Design/methodology/approach -The paper proposes a new substrate network 3D extraction technique, adapted from a transmission line method or Green kernels, but in the whole volume. Findings -Extracting impedances between any numbers of embedded contacts with variable shapes or/and through silicon via. This 3D method is much faster comparing with FEM Originality/value -Previous works consider TSVs alone, contacts onto the substrate. The authors do study entanglement between the substrate and the interconnections.

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