Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

Qiao, Ming; Wang, Yuru; Li, Yanfei; Zhang, Bo; Li, Zhaoji

doi:10.1016/j.spmi.2014.09.009

Cited by 11 publications

(2 citation statements)

References 26 publications

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“…Scholars have obtained many results after long-term research on StBV. Some of these results have been obtained using an analytical model of StBV [8][9][10][11][12][13][14], and others are related to new structures [15][16][17][18][19][20][21][22][23][24][25][26][27], in some of which StBV can reach more than 1000 V [25][26][27]. However, when a device is turned off rapidly, there is insufficient time for an electron inversion layer to form under the BOX, which can induce a DD effect in the Micromachines 2023, 14, 887 2 of 14 substrate.…”

Section: Introductionmentioning

confidence: 99%

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

et al. 2023

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In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

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Section: Introductionmentioning

confidence: 99%

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

et al. 2023

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“…Regarding the static breakdown voltage (StBV) of silicon-oninsulator (SOI) lateral double-diffused metal-oxidesemiconductor (LDMOS), when the device is in the off state, there is an inversion layer under the buried oxide (BOX), and the blocking voltage can only be sustained by the drift region and the BOX [1]- [2]. Due to the limitation of the device's vertical dimension, it is difficult for conventional SOI LDMOS to obtain a BV higher than 600 V. To allow SOI LDMOS to be used in high voltage integrated circuits, many new device structures have been proposed [3]- [15], some with breakdown voltages (BVs) exceeding 1000 V [13]- [15]. However, these high voltage structures are all based on the research results of StBV.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Yang

Cao

et al. 2020

IEEE Access

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With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (Nd) and substrate doping concentration (Psub) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (Vd), the turn-off nonbreakdown time (Tnonbv) of the device with higher Psub decreases faster. However, the Tnonbv with higher Psub is higher at low Vd. Therefore, the maximum Tnonbv can be obtained by optimizing Nd and Psub under a given Vd. In addition, Tnonbv is greatly reduced with increasing temperature.INDEX TERMS Silicon-on-insulator (SOI), MOS devices, deep depletion (DD), breakdown voltage (BV).

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Improvement the Breakdown Voltage and the On-resistance in the LDMOSFET: Double Buried Metal Layers Structure

Shoormasti

Abbasi

Orouji

2020

Silicon

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Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

Cited by 11 publications

References 26 publications

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Improvement the Breakdown Voltage and the On-resistance in the LDMOSFET: Double Buried Metal Layers Structure

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