2018 IEEE International Power Modulator and High Voltage Conference (IPMHVC) 2018
DOI: 10.1109/ipmhvc.2018.8936701
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Charge Plasma High Voltage PIN Diode Investigation

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Cited by 3 publications
(2 citation statements)
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“…Nanoscale p-n diode was a primary device that is designed and fabricated applying this technique [3], [4], [5]. Doping-less bipolar transistors (BJTs), Schottky collector bipolar transistor without impurity doped emitter and base [6], [7], [8], [9], laterally singled-diffused metal oxide semiconductor, Junction-less Impact Ionization MOS, Doping-less tunnel field effect transistor and high voltage devices such as strained super-junction vertical single diffused MOSFET, silicon-based 50 V p-i-n diode [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22] are designed utilizing charge plasma concept which not only reduces the process of fabrication, but in some cases results in a better performance as compared with the conventional (doped) counterparts.…”
Section: Introductionmentioning
confidence: 99%
“…Nanoscale p-n diode was a primary device that is designed and fabricated applying this technique [3], [4], [5]. Doping-less bipolar transistors (BJTs), Schottky collector bipolar transistor without impurity doped emitter and base [6], [7], [8], [9], laterally singled-diffused metal oxide semiconductor, Junction-less Impact Ionization MOS, Doping-less tunnel field effect transistor and high voltage devices such as strained super-junction vertical single diffused MOSFET, silicon-based 50 V p-i-n diode [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22] are designed utilizing charge plasma concept which not only reduces the process of fabrication, but in some cases results in a better performance as compared with the conventional (doped) counterparts.…”
Section: Introductionmentioning
confidence: 99%
“…Nano scale p-n diodes have been designed and fabricated using charge plasma concept [2], [3], [4]. Lateral and vertical bipolar junction transistors (BJTs) [5], [6], [7], [8], LSMOS, SJ VSDMOS, transistirs, Bi-directional Junction-less Transistor, PIN diode, IMOS, TFETs [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20]. The CP approach not only reduces the fabrication complexity but also results in an improved performance.…”
Section: Introductionmentioning
confidence: 99%