Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Wu, Xiaoxia; Zhao, Wei; Nakamoto, Mark; Nimmagadda, Chandra; Lisk, D.; Gu, Sam; Radojcic, Riko; Nowak, Matt; Xie, Yuan

doi:10.1109/tvlsi.2010.2090049

Cited by 39 publications

(18 citation statements)

References 12 publications

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“…[95][96][97] The equivalent TSV self-capacitance is an important parameter for RC delay, which needs to be considered during TSV design. The equivalent TSV inductance is also important for interconnect performance such as SSN that is determined by TSV length.…”

Section: Temperature Distribution and Thermal Stressesmentioning

confidence: 99%

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

Kumar

2014

Applied Physics Reviews

126

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Section: Temperature Distribution and Thermal Stressesmentioning

confidence: 99%

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

Kumar

2014

Applied Physics Reviews

126

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“…Additionally, in the most commonly used face-to-back (F2B) bonding technology, TSVs must tunnel through the substrate of one tier [21]. Under the current technology, TSVs are usually much larger than the vias in the metal layers, so they should be placed in the whitespace between the modules in the device layer.…”

Section: B Our Motivationmentioning

confidence: 99%

“…The TSV model we adopt is shown in Figure 2 [23]. R t and C t represent the parasitic resistance and capacitance of one P/G TSV respectively.…”

Section: A Modeling Of 3d Power Delivery Networkmentioning

confidence: 99%

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Efficient region-aware P/G TSV planning for 3D ICs

Song

Chen

Wang

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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Power delivery network (PDN) design is one of the most critical challenges in 3D Integrated Circuits (IC) design. In existing studies, to ensure the robustness of the 3D PDN, the number of TSVs was always increased inefficiently to mitigate the IR-drop and power noise. However, the overhead for connections is a crucial obstacle to the development of 3D ICs. Consequently, an efficient TSV topology is needed to reduce the overhead of TSVs while meeting the power supply requirements. The redundant TSVs may introduce more keepout zones, decrease the core utilization of the chip, and lead to high cost. In this paper, we propose a region-aware TSV planning algorithm which can distribute TSV resources non-evenly over different areas according to their IR-drop constraints separately. This method can use fewer power TSVs to meet the power integrity constraint of the whole chip while guaranteeing the functionality. Furthermore, to ensure the practicability, we also take the whitespace into account. Experimental results show that, the proposed algorithm can save on average 42% and 27% power TSV resources without and with whitespace consideration respectively compared with the evenly TSV planning algorithm.

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“…However the physical limits restrict the reduction of transistor size [1]. And there are problems of delay, power and parasitic effects as technology develops.…”

Section: Introductionmentioning

confidence: 99%

A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC

Deng¹,

Zhang²,

Li³

2015

Advances in Intelligent Systems Research

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Abstract. As the technology of three dimension integrated circuit (3D IC) develop quickly, through silicon via (TSV) plays a basic and important role.In consideration of real working environment, factors as temperature and working voltage are studied by TCAD simulator. And the contribution of physical sizes and the concentration of doping in the course are analyzed. A new analysis model of capacitance for TSV is given, which is with an error less than 4% with the measurement data. In the range of 25 to 125 degree centigrade with different physical sizes of TSV, this model of TSV's parasitic capacitance shows a better accuracy and takes less time than the former one. The neglect of temperature in course of design will lead to a big problem in real chip, an accurate mode considering temperature is important both in design and SI analysis.

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Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Cited by 39 publications

References 12 publications

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

Efficient region-aware P/G TSV planning for 3D ICs

A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC

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