Efficient region-aware P/G TSV planning for 3D ICs

Song, Yong; Chen, Xiaoming; Wang, Yu; Ma, Yuchun; Xie, Yuan; Yang, Huazhong

doi:10.1109/isqed.2014.6783321

Cited by 6 publications

(2 citation statements)

References 23 publications

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“…Decoupling capacitance insertion for 3-D power grid optimization is explored in [30]. Planning and placement of power and ground TSVs were investigated in [31].…”

Section: A Contributions Of This Papermentioning

confidence: 99%

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Todri‐Sanial

Cheng

2016

IEEE Trans. VLSI Syst.

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Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.Index Terms-3-D ICs, clock networks, power and thermal integrity, power delivery networks (PDNs), through-siliconvias (TSVs).

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“…Decoupling capacitance insertion for 3-D power grid optimization is explored in [30]. Planning and placement of power and ground TSVs were investigated in [31].…”

Section: A Contributions Of This Papermentioning

confidence: 99%

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Todri‐Sanial

Cheng

2016

IEEE Trans. VLSI Syst.

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“…However, the PIG TSVs were regularly distributed for each layer due to the incomplete power profile. Compared to the regular one, the irregular TSV distribution topology provides a superiority in terms of power supply noise, TSV number, and footprint area [2], [3], [16]. Therefore, a novel design methodology was proposed in [3], in which the planning of PIG TSVs was performed on a detailed layout.…”

mentioning

confidence: 99%

Stress-aware P/G TSV planning in 3D-ICs

Wang

Firouzi

Oboril

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of PIG TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates.Thus, it is necessary to consider the combined effect on delay variation during the PIG TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined PIG TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the PIG TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches.

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