Efficient FPGAs using nanoelectromechanical relays

Chen, Chen; Parsa, Roozbeh; Patil, Nishant; Chong, Soogine; Akarvardar, K.; Provine, J.; Lewis, David; Watt, J.T.; Howe, Roger T.; Wong, H.-S. Philip; Mitra, Subhasish

doi:10.1145/1723112.1723158

Cited by 66 publications

(32 citation statements)

References 19 publications

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“…Cell Architecture Figure 3 presents the three-dimensional view of two adjacent NEMsCAM cells located in the same column index of the CAM array. Since NEMs have the potential to be fully integrated with CMOS devices [9], we place them on top of the CMOS layer and substantially reduce the layout area. The SL wires run parallel to the BL wires, while the matchlines (ML) and wordlines (WL) are orthogonal to the BLs.…”

Section: A Circuit Operationsmentioning

confidence: 99%

“…However, NEMs have relatively long mechanical switching delay [6] compared to the intrinsic delay of CMOS devices, and to this date, they suffer from low endurance [15]. To get the best of both worlds, researchers have combined NEMs and CMOS to build low-power and high performance circuits for critical components [9], [10].…”

Section: Introductionmentioning

confidence: 99%

“…Since NEMs can be fully integrated with CMOS devices [9], we locate them on top of the CMOS device layer reducing considerably the layout area and the energy consumption. To our knowledge, we are the first to design such a CAM cell.…”

Section: Introductionmentioning

confidence: 99%

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NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

Seyedi

Karakostas

Cosemans³

et al. 2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

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Abstract-In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nanoelectro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOSonly TLB with minimal performance overhead.

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Section: A Circuit Operationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

Seyedi

Karakostas

Cosemans³

et al. 2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

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“…Various approaches have been taken to reduce this overhead. In [15], a nanoelectromechanical relay replaced the NMOS pass transistors in a switch matrix. More conventional approaches have tried to optimize the global interconnect architecture since their performance dominates the delay and energy of the FPGA [17]- [19].…”

Section: B Chip Implementationmentioning

confidence: 99%

Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects

Lee

Park

Kong

et al. 2013

IEEE Trans. Electron Devices

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Abstract-We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-μm CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11× faster speeds and 1.54× lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using lowcapacitance graphene wires for ultralow power electronics.

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“…Die-stacking introduces undesirable problems in terms of manufacturability, reliability and limit of the vertical integration density. Some researchers replace the pass transistors in the routing structure of FPGA with emerging memory elements integrated in metal layers with back-end-of-line (BEOL) compatible fabrication [20,21]. But the improvement is limited due to the small portion of pass transistors in the routing structure.…”

Section: B Recent Work On Fpgas Using Emerging Technologiesmentioning

confidence: 99%

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Cong

Xiao

2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

115

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Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.

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Efficient FPGAs using nanoelectromechanical relays

Cited by 66 publications

References 19 publications

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

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