Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Abe, Mari; Furutake, N.; Saito, Shinobu; Inoue, N.; Hayashi, Y.

doi:10.1143/jjap.44.2294

Cited by 10 publications

(10 citation statements)

References 17 publications

(15 reference statements)

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“…Since the lifetime of a via chain is determined by the void that grows the quickest, the comparison between eqs. (8) and (14) explains the observations in Fig. 3 where most all of the voids are connected to grain boundaries.…”

Section: Effect Of Grain Boundary Beneath Via On Stress-inducedmentioning

confidence: 57%

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Tsuchikawa

Mizushima

Nakamura

et al. 2006

jjap

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Many observations of stress-induced voids beneath vias in wide Cu lines have been performed to analyze stress migration phenomena. Most of the voids that caused fatal failures of circuits accompanied grain boundaries in the lower lines. Finite element method calculations were performed to obtain the stress distribution around a via sandwiched between wide upper and lower lines. Based on these results, a void growth model for the Cu stress migration phenomena has been proposed by applying the Hull and Rimmer theory. This model takes two diffusion paths, such as a grain boundary and a barrier/Cu interface, into consideration. Compared with experimental results, the proposed model successfully explained the mean time to failure dependence on the temperature and geometrical parameters of Cu interconnects.

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Section: Effect Of Grain Boundary Beneath Via On Stress-inducedmentioning

confidence: 57%

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Tsuchikawa

Mizushima

Nakamura

et al. 2006

jjap

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“…The deep-tapered via after the SiV test had a wedge void in the wide M1 line under the via as the M1-mode SiV failure, where a grain boundary existed under the via as the vacancy pipeline. 13,14) Namely, from the SiV test, it is found that the M1-mode SiV failure strongly depended on the via profile, which might be affected by the mechanical stress gradient around the via.…”

Section: Impact Of Via Profile On Siv Reliabilitymentioning

confidence: 99%

“…12) Few papers, however, have discussed the effects of the via shape and the DD fabrication processes on the SiV reliability. [13][14][15] In this study, we investigated the effect of the via taper angles on the SiV reliability in monolithic Cu DDIs with a molecular-pore-stack (MPS) SiOCH film. 1) Therefore, a special DD etching process is developed to control the via profile such as the top and bottom taper angles, and three different via profiles are fabricated; i.e., (1) the shallowtapered vias, (2) the stepped vias, and (3) the deep-tapered vias with a via-bottom diameter of 70 nm.…”

Section: Introductionmentioning

confidence: 99%

Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects

Kume¹,

Inoue²,

Saito³

et al. 2010

Jpn. J. Appl. Phys.

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We estimate how well we will know the parameters of solar neutrino oscillations after KamLAND and Borexino. The expected error on ∆m 2 is few per-mille in the VO and QVO regions, few per-cent in the LMA region, and around 10% in the LOW region. The expected error on sin 2 2θ is around 5%. KamLAND and Borexino will tell unambiguously which specific new measurement, dedicated to pp solar neutrinos, is able to contribute to the determination of θ and perhaps of ∆m 2 . The present data suggest as more likely outcomes: no measurement, or the total pp rate, or its day/night variation.

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“…The effect of increasing the thermal budget on interconnect reliability has become a concern, and the effects of thermal processes on stress-induced voiding (SIV) have been studied. [2][3][4] Copper electromigration (EM) has been studied extensively, 5,6) but its effect on EM reliability has been less studied.…”

Section: Introductionmentioning

confidence: 99%

Degradation of Electromigration Lifetime of Cu/Low-k Interconnects by Postannealing

Kakuhara

Ueno

2009

jjap

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The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and its effect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.

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Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Cited by 10 publications

References 17 publications

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects

Degradation of Electromigration Lifetime of Cu/Low-k Interconnects by Postannealing

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