Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Abstract

Many observations of stress-induced voids beneath vias in wide Cu lines have been performed to analyze stress migration phenomena. Most of the voids that caused fatal failures of circuits accompanied grain boundaries in the lower lines. Finite element method calculations were performed to obtain the stress distribution around a via sandwiched between wide upper and lower lines. Based on these results, a void growth model for the Cu stress migration phenomena has been proposed by applying the Hull and Rimmer theory. This model takes two diffusion paths, such as a grain boundary and a barrier/Cu interface, into consideration. Compared with experimental results, the proposed model successfully explained the mean time to failure dependence on the temperature and geometrical parameters of Cu interconnects.

Void Growth Behavior in ULSI Cu Interconnections by Grain-Boundary Diffusion Simulation

“…Therefore, SIV is recognized as a serious problem that can compromise the reliability of Cu interconnections. [4][5][6][7][8] SIV tends to be generated close to the bottom of the via holes, as shown in Fig. 1.…”

“…Void Growth Behavior in ULSI Cu Interconnections by Grain-Boundary Diffusion Simulation Therefore, the normalized atomic flux, " J a ; can be obtained from matrix (8) where " c m is defined as " c m ¼ c À À c þ ð Þ 2 " l; and c + and c À are the lengths of voids or cracks that progress along the grain boundary from the positive or negative ends of the grain boundary. If a void exists at the end of a grain boundary, c is equivalent to the radius of the void.…”

Ultra thermal stability of LED die-attach achieved by pressureless Ag stress-migration bonding at low temperature

“…A phenomenon so called "stress migration" in metallic thin-films arises from the mechanical stress accompanied by diffusional plastic deformation of the films [10][11][12][13][14][15][16][17][18][19][20]. When thermally activated, atoms and vacancies in stressed thin-films may easily diffuse to reduce the internal stress, and generate protrusions like hillocks and whiskers on the surface, or form internal voids as well.…”

A Study of Difference in Reflow Characteristics Between Electroplated and Sputtered Cu in a Dual-Damascene Fabrication Process for Silicon Semiconductor Devices

“…These defects are recognized as a serious problem, since they degrade the electronic properties and reduce the reliability of the interconnections. [4][5][6][7][8][9][10][11] The width of the interconnections in ULSI devices is gradually shrinking; therefore, it is becoming more difficult to perfectly fill extremely small vias and trenches (with diameters or widths of 100 nm or less) by Cu electroplating.…”