Thermal stress-induced void formation in aluminum interconnect has become a major reliability problem in the usage of very large scale integration circuits. The purpose of this work is to analytically evaluate stresses in the Al line. By applying Eshelby’s method in micromechanics, the stresses in the Al line were estimated analytically as a function of the aspect ratio of the Al line cross section. The yielding criteria in plasticity were applied to examine whether the calculated stresses can induce relaxation by plastic deformation. The analytically calculated results were compared with previous results of numerical calculation and experimental observation.

Using the previously obtained stress distributions in an Al line after relaxation by plastic deformation, another possible relaxation process by diffusion was analyzed. Even after this relaxation occurs, some stresses still remain in the Al line. If these remaining stresses are large enough, they can be responsible for the growth of voids causing line failure. Using a theory for diffusional growth of grain-boundary voids, the time to failure of the Al line was estimated analytically. The previous and present papers together constitute a full analysis of the so-called ‘‘stress migration’’ phenomenon.

When manufacturing prototype devices or low volume custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We attempt to apply EBDW mainly to critical interconnect layers to reduce the mask expenditure for the reason of technical output reusability.For 65nm node production, new 300mm EB direct writer had been installed. The process technologies have also been developing to meet sufficient qualities and productivities.

Many observations of stress-induced voids beneath vias in wide Cu lines have been performed to analyze stress migration phenomena. Most of the voids that caused fatal failures of circuits accompanied grain boundaries in the lower lines. Finite element method calculations were performed to obtain the stress distribution around a via sandwiched between wide upper and lower lines. Based on these results, a void growth model for the Cu stress migration phenomena has been proposed by applying the Hull and Rimmer theory. This model takes two diffusion paths, such as a grain boundary and a barrier/Cu interface, into consideration. Compared with experimental results, the proposed model successfully explained the mean time to failure dependence on the temperature and geometrical parameters of Cu interconnects.