Effects of “fast” rapid thermal anneals on sub-keV boron and BF2 ion implants

Downey, Daniel F.; Falk, S.; Bertuch, Adam; Marcus, S.

doi:10.1007/s11664-999-0119-6

Cited by 24 publications

(9 citation statements)

References 4 publications

(5 reference statements)

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“…This work was supported by SRC and SEMATECH. The review of this paper was arranged by Editor C. McAndrew Experiments show increasing the ramp rate during thermal processing has been shown to decrease the TED of boron in silicon [9]- [11]. Plots of the ramp up rate versus diffusion length show that the ramp up rate would need to be around 10 C/s to result in a diffusion length of zero, and hence no TED [12].…”

Section: Introductionmentioning

confidence: 99%

Nonmelt laser annealing of 5-KeV and 1-KeV boron-implanted silicon

Earles

Law

Brindos

et al. 2002

IEEE Trans. Electron Devices

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Abstract-Nonmelt laser annealing has been investigated for the formation of ultrashallow, heavily doped regions. With the correct lasing and implant conditions, the process can be used to form ultrashallow, heavily doped junctions in boron-implanted silicon. Laser energy in the nonmelt regime has been supplied to the silicon surface at a ramp rate greater than 10 C/s. This rapid ramp rate will help decrease dopant diffusion while supplying enough energy to the surface to produce dopant activation. High-dose, nonamorphizing boron implants at a dose of 10 ions/cm and energies of 5 KeV and 1 KeV are annealed with a 308-nm excimer laser. Subsequent rapid thermal anneals are used to study the effect of laser annealing as a pretreatment. SIMS, sheet resistance and mobility data have been measured for all annealing and implant conditions. For the 5-KeV implants, the 308-nm nonmelt laser preanneal results in increased diffusion. However, for the 1-KeV implant processed with ten laser pulses, the SIMS profile shows that no measurable diffusion has occurred, yet a sheet resistance of 420 /sq was produced.

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Section: Introductionmentioning

confidence: 99%

Nonmelt laser annealing of 5-KeV and 1-KeV boron-implanted silicon

Earles

Law

Brindos

et al. 2002

IEEE Trans. Electron Devices

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“…The results from this work are compared to recently reported ion implanted and annealed layers [19][20][21][22] in Fig. 4.…”

Section: Discussionmentioning

confidence: 90%

Formation of p+ shallow junctions using SiGe barriers

Thompson

Crosby

Bennett³

et al. 2004

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Ultrashallow p+ junctions are required for next generation electronics. We present a technique for the formation of ultrashallow p+ junctions that increases the thermal stability of the junctions formed by either epitaxy or ion implantation. By using a 10nm Si1−xGex barrier layer, the diffusion of B is inhibited during high temperature processes. Alloys having a composition from x=0–0.4 were investigated and it is shown that the most effective barrier had the maximum Ge fraction. The junction depth decreased to 36.7nm for a 5×1015∕cm2 1kV BF3 plasma implant spike annealed at 1050°C, compared to a junction depth of 48nm for a Si control sample having the identical implant and anneal. It is hypothesized that the inhibition of B diffusion in the alloy layer is caused by a reduction of the Si self-interstitials in the alloy.

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“…In addition, it has been shown that a controlled ambient of 33 ppm oxygen in a nitrogen purge is the optimal environment for ultrashallow dopant annealing [1]. This tightly controlled, low-oxygen ambient allows just enough of a surface oxide to be grown to limit the out-diffusion of boron from the wafer while consuming a minimal amount of silicon during the oxidation process.…”

Section: Resultsmentioning

confidence: 99%

“…The most pressing application of RTP is the formation of the S/D regions of the CMOS gate stack. Device operation is optimal when these doped regions are kept as box-shaped as possible [1], [2]. Deviation from this box-shaped profile reduces the ratio increases threshold voltage rolloff, detrimentally reduces the minimum gate length, and increases the gate-drain capacitance.…”

Section: Introductionmentioning

confidence: 99%

Electromagnetic annealing for the 100 nm technology node

Thompson

Booske

Gianchandani

et al. 2002

IEEE Electron Device Lett.

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Abstract-Electromagnetic induction heating (EMIH) is a novel rapid thermal processing technique that uses microwave and radio frequency (RF) radiation to directly heat silicon wafers. Heating rates of 125 C/s have been achieved and 75 mm diameter wafers have been heated above 1000 C using only 950 W of power. EMIH has been used to activate shallow implanted dopants with minimal diffusion of the junction depth. It is speculated that the exposure of the wafer to intense electric fields during the anneal may provide an additional driving force for dopant activation, allowing for higher activation at lower temperatures. Post-anneal junction depths less than 25 nm with sheet resistances between 700 and 1000 ohms/square have been achieved without the use of a controlled low oxygen ambient. The EMIH Rs-Xj curve penetrates the SE-MATECH 100 nm technology box and with further optimizations may satisfy the 70 nm technology node.

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Effects of “fast” rapid thermal anneals on sub-keV boron and BF2 ion implants

Cited by 24 publications

References 4 publications

Nonmelt laser annealing of 5-KeV and 1-KeV boron-implanted silicon

Nonmelt laser annealing of 5-KeV and 1-KeV boron-implanted silicon

Formation of p+ shallow junctions using SiGe barriers

Electromagnetic annealing for the 100 nm technology node

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