Ion implants of 1 keV B+11 and 5 keV BF2+, to a dose of 1×1015/cm2 at a tilt angle of 0°, were implanted into preamorphized (Si+,70 keV, 1×1015/cm2) wafers. These samples were rapid thermal annealed in an ambient of 33 ppm of oxygen in N2 at very short times (<0.1 s spike anneals) at 1000 and 1050 °C to investigate the effects of the fluorine in BF2 implants on transient enhanced diffusion (TED). By using a relatively deep preamorphization of 1450 Å, any difference in damage between the typically amorphizing BF2 implants and the nonamorphizing B implants is eliminated because the entire profile (<800 Å after annealing) is well contained within the amorphous layer. Upon annealing, the backflow of interstitials from the end-of-range damage from the preamorphization implant produces TED of the B in the regrown layer. This allows the chemical effect of the fluorine on the TED of the B in the regrown Si to be studied independent of the damage. The secondary ion mass spectroscopy results show that upon annealing, the presence of fluorine reduces the amount of B diffusion by 30% for the 1000 °C spike anneal, and by 44% for the 1050 °C spike anneal. This clearly illustrates there is a dramatic effect of F on TED of B independent of the effects of implant damage. Analysis of the temperature dependence of the enhancement factors point to transient enhanced diffusion not boridation as the source of the interstitials.
The use of flash lamp annealing for ultrashallow junction formation in silicon has been described. Low energy boron and arsenic implants have been heat-treated in this way using peak temperatures in the range of 1100 to 1300°C and effective anneal times of 20 and 3 ms. Secondary ion mass spectrometry and four-point probe measurements have been undertaken to determine the junction depth and the sheet resistance, respectively. Optimum processing conditions have been identified, under which one can obtain combinations of junction depth and sheet resistance values that meet the 90 nm technology node requirements and beyond.Source/drain junction depths need to be reduced in line with the continuing scaling down of deep submicrometer devices in silicon. Currently, the technique of choice for producing ultrashallow junctions ͑USJs͒ that meet the specifications of the sub-90 nm node relies on the use of ultralow energy boron ion implantation followed by extremely short time thermal annealing. 1-3 The key structural parameters of a USJ are the sheet resistance R s and junction depth X j . According to the International Technology Roadmap for Semiconductors (ITRS) 2003 4 the realization of the 90 nm node, whose year of production is 2004, calls for R s ഛ 663 ⍀/ᮀ and X j ഛ 20.4 nm. The respective values for the 65 nm node, which is scheduled for the year 2006 are R s ഛ 884 ⍀/ᮀ and X j ഛ 13.8 nm.Thermal annealing techniques such as rapid thermal processing ͑RTP͒ and, more recently, spike RTP 1-3,5,6 have been adequate to control the processing of mainstream devices. These annealing methods, however, will soon become unsuitable for the USJs required in the near future. The reason is that the effective anneal times 7 used are still relatively long, being in the order of 1 s or more. The fabrication of USJs necessitates both very high annealling temperatures for achieving high electrical activation, and extremely short times of heat-treatment to minimize the effect of dopant transient enhanced diffusion ͑TED͒ 8 responsible for the undesirable junction broadening. The attempts to meet these two competing requirements have led to great interest in the development of alternative ultrafast heat-treatment methods, of which laser thermal processing ͑LTP͒ 9 and flash-assisted RTP ͑fRTP™͒ 10,11 are presently among the most promising ones.The common feature of all ultrafast thermal annealing processes is the use of a small thermal budget involving a high peak temperature, T max , coupled with a very short effective time of the anneal cycle and very high ramp-up/cool-down rates. LTP has some inherent problems associated with dopant deactivation and process integration. In fRTP™, the device structure is exposed to a short duration pulse or flash ͑on the order of milliseconds͒ of intense light produced by an arc lamp.We have developed and tested successfully an alternative version of ultrarapid thermal processing based on the use of a xenon flash lamp system, hereafter referred to as the flash lamp annealing ͑FLA͒ technique. Results of a p...
The solid phase epitaxial growth technique appears to be a promising method for achieving junction depths and sheet resistance values low enough to meet the performance specifications of the 65 and 45 nm node for boron, BF 2 , and BF 3 doping profiles in amorphous silicon. Room-temperature implants of these three dopant species into Si͑100͒ preamorphized by 74 Ge + ͑30 keV, 1.0 ϫ 10 15 cm −2 ͒ lead to boron concentration profiles that fulfill the technological requirements. It was found that even for ultrashallow junctions the time for the regrowth process at 650°C has to be optimized with regard to the implanted species in the range between 5 and 60 s, especially when fluorine is present. The thermal stability of the boron profile distribution that meets 65-nm-node requirements was evaluated by subsequent thermal anneals simulating the thermal effects expected for typical silicidation processes. For a more detailed investigation, the postannealing temperatures ranged from 250 to 1050°C with times from a few to several hundred seconds. All the junctions were analyzed by four-point probe and selected samples by secondary ion mass spectroscopy, transmission electron microscopy, and high-resolution electron microscopy.The combination of doping and activation technology is expected to provide solutions for highly activated, shallow, and abrupt dopant profiles required for advanced logic device technology beyond the 90-nm node. 1 In contrast to spike and/or flash annealing, a simple approach for the formation of ultrashallow junctions with boron consists of preamorphizing the substrate prior to dopant implantation followed by a low-temperature solid phase epitaxial growth process ͑SPEG͒. The SPEG technique currently appears to be a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65-and 45-nm node. The optimal process for high activation during SPEG involves annealing at ϳ650°C for 5-60 s in an inert ambient. 2 The main advantages of the SPEG technique is that it has been extensively studied for at least three decades. In general it is rather simple and requires only conventional implant and rapid thermal processing equipment. It is also a low-temperature approach that is thermally compatible with advanced materials such as high-k dielectrics and metal gates. In this paper we present some of our recent results on the formation of ultrashallow junctions using the SPEG technique. Additionally, data for technology nodes beyond 90 nm are also presented in a sheet resistance vs junction depth matrix, including data from current literature of various techniques.However, the thermal stability of activated junctions is a critical consideration for front-end complementary metal oxide semiconductor ͑CMOS͒ manufacturing. Therefore, in the second part we present a detailed study of boron deactivation during thermal processes after SPEG. Postannealing temperatures were chosen in order to "simulate" typical self-aligned silicide processes for NiSi or...
There has been considerable interest recently, in the formation of the source drain junctions of metal oxide semiconductor transistors using solid phase epitaxy (SPE) to activate the dopants rather than a traditional high temperature anneal. Previous studies have shown that this method results in high dopant activation as well as shallow junctions (due to the small thermal budget). In this we study the effect the temperature of SPE regrowth has on the boron activation. We find that boron activation has a monotonically increasing dependence on the temperature. Significantly, we show that by carrying out the SPE regrowth at temperatures above 1050°C, it is possible to obtain active concentrations well above the electrical solubility limits.
Ion implants of 1.0 keV 11B+, 5 keV BF 2+, and 2.0 keV As+ at a dose of IeI5/cm2 were rapid thermal annealed (RTA) in a STEAG AST-2800µ with varying percents of oxygen in N2, ranging from 0-lppm to 50,000 ppm to investigate the effects of low concentrations of oxygen during anneal. Sheet resistance (Rs), ellipsometry, SIMS, Tapered Groove Profilometry (TGP), and Scanning Force Microscopy (SFM) were employed to characterize these layers. For each of these implant cases, an optimal RTA condition is established which maximizes retained dose while still producing shallow junctions. As a function of O2 content, anneal temperature and implant condition, three regimes are observed that affect after anneal retained dose. These regimes are: dopant loss to the ambient resulting from etching of Si, dopant loss by out-diffusion from evaporation/chemical reactions, a capping regime that minimizes out-diffusion. In this later regime the dopant loss results from consumption into the RTA grown oxide. In addition, this paper also discusses oxidation enhanced diffusion (OED) and identifies its extent as a function of temperature and O2 content of the anneal for the three implant conditions investigated. For example, a 1.0 keV 11B+wafer annealed at 1050°C lOs in a controlled 33 ppm of O2 in N2 yields a SIMS junction depth 320 Å shallower than previously reported by others.
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