Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

Abstract

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

On-chip Hot Spot Remediation with Miniaturized Thermoelectric Coolers

“…The results displayed in Fig. 5 for 3.6 mm × 3.6 mm and 1.3 mm × 1.3 mm mini-contact sizes, showed very close agreement between the FEM simulations and experiments and revealed that, despite the relatively high contact resistance (9 × 10 −6 m 2 K/W and 8.5 × 10 −5 m 2 K/W for the 3.6 × 3.6mm 2 and 1.3 × 1.3mm 2 mini-contact tests, respectively) significant cooling of nearly 8 • C could be achieved with this configuration (Litvinovitch and Bar-Cohen 2009). Using the calibrated FEM model, the effect of the chip thickness and contact resistance on hot spot cooling performance of the mini-contact TEC was evaluated.…”

On-chip Peltier cooling using current pulse

“…For ultrathin modules used for the micro-electronic packages as in [1], the electrical and thermal resistances at the superlattice-metal interface and at TEC module-spreader interface can drastically degrade the performance of TECs [1]. There are some recent attempts to understand the effect of these contact resistances [11]. A detailed study of pulsed cooling in the context of use of ultra-thin TEC modules on the active side of the electronic package has not been performed.…”

Array of Thermoelectric Coolers for On-Chip Thermal Management

“…The thermal and electrical contact resistances at the TEC's interfaces are affected by the fabrication process and are considered as the most critical parameters affecting the device performance [13]. High electrical and thermal contact resistances significantly degrade the performances of these devices [14,15].…”

“…Chip-scale integration requires ultrathin TEC modules where electrical and thermal contact resistances at the super-latticemetal interface and the TEC module-spreader interface can affect the TEC performance [2]. Some efforts have been made to study the effect of these parasitic resistances and it has been suggested that the impact of contact resistance can be much more pronounced for thermoelectric coolers of length of the order of 100 lm or smaller [14,15,23]. Wang et al have studied the effects of various crucial contact parameters such as electrical contact resistance on the performance of silicon based thermoelectric microcoolers.…”