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The high-field properties of carbon nanotube (CNT) network thin film transistors (CN-TFTs) are important for their practical operation, and for understanding their reliability. Using a combination of experimental and computational techniques we show how the channel geometry (length L C and width W C ) and network morphology (average CNT length L t and alignment angle distribution θ) affect heat dissipation and high-field breakdown in such devices. The results suggest that when W C ≥ L t , the breakdown voltage remains independent of W C but varies linearly with L C . The breakdown power varies almost linearly with both W C and L C when W C >> L t . We also find that the breakdown power is more susceptible to the variability in the network morphology compared to the breakdown voltage. The analysis offers new insight into the tunable heat dissipation and thermal reliability of CN-TFTs which can be significantly improved through optimization of the network morphology and device geometry.

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

We study the impact of thermal boundary conductance (TBC) at carbon nanotube (CNT)-substrate interfaces and CNT junctions on power dissipation and breakdown in CNT network based thin film transistors (CN-TFTs). Comparison of our results from an electro-thermal transport model of CN-TFTs to experimental measurements of power dissipation and temperature profiles allows us to estimate the average CNT-SiO 2 TBC as g $ 0.16 Wm À1 K À1 and the TBC at CNT junctions as G C $ 2.4 pWK À1. We find the peak power dissipation in CN-TFTs is more strongly correlated to the TBC of the CNT-substrate interface than to the TBC at CNT junctions. Molecular dynamics simulations of crossed CNT junctions also reveal that the top CNT is buckled over $30 nm lengths, losing direct contact with the substrate and creating highly localized hot-spots. Our results provide new insights into CNT network properties which can be engineered to enhance performance of CN-TFTs for macro and flexible electronics applications. V

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