Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

Noor, Samantha Lubaba; Safa, Samia; Khan, Md. Ziaur Rahman

doi:10.1007/s10825-016-0816-3

Cited by 24 publications

(12 citation statements)

References 28 publications

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“…Owing to the band-to-band tunneling (BTBT) mechanism, Tunnel field-effect transistors (TFETs) allow further scaling of operation voltages, which makes them the most promising alternatives to the conventional metal oxide semiconductor field-effect transistors (MOSFETs) for low-power applications [1,2,3,4]. However, the All-silicon TFET suffers from unacceptably low on-state current, which is even lower than the demand reported by the International Technology Roadmap for Semiconductors (ITRS) [5,6], due to the indirect and large bandgap and thus its practical use is retarded.…”

Section: Introductionmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

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Section: Introductionmentioning

confidence: 99%

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Zhang

et al. 2019

Nanomaterials

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“…Modeling and simulation of TFET plays an important role to understand the device characteristic. Analytical model of DMDG TFET proposed by Arun Samuel and Balamurugan, Vishnoi and Kumar, and Noor et al solved the Poisson equation using the parabolic approximation method. Analytical model using the superposition approximation method were reported by Lee and Choi for single gate TFET and Gholizadeh and Hosseini for DG TFET.…”

Section: Model Formulationmentioning

confidence: 99%

“…Solving for the above equation for electric field, we obtain the values of the vector components of the electric field as Ey 1 (x, y) and Ey 2 (x, y); taking root mean square value of these vector components of electric field, we get E y (x, y) as 1.32×10 6…”

Section: Calculation Of Electrostatic Potentialmentioning

confidence: 99%

Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method

Jossy

Vigneswaran

Malarvizhi

et al. 2018

Concurrency and Computation

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Summary Tunnel field effect transistors are used for ultra‐low power application since it is challenging to operate CMOS at very low supply voltage. As tunnel field effect transistor has a very low subthreshold slope due to band to band tunneling (BTBT) mechanism, it has the potential to operate at very low operating voltage. It is necessary that the devices utilized in implantable bio‐medical applications and Internet of Everything (IoE) need to consume very low power. This work presents an analysis of Dual Material Double Gate Tunnel Field effect transistor (DMDG‐TFET). An analytical two dimensional (2D) model has been developed to obtain the analytical expressions for drain current. The 2D Poisson's equation has been used to calculate surface potential in the silicon channel using the superposition approximation, as it considers the short channel effects in the calculation of the current when compared to parabolic approximation. To validate the model, analytical results have been confirmed by comparing with the Sentaurus TCAD simulation results. A reduced subthreshold slope of 31.2 mV/decade is obtained in this paper. It shows that DMDG TFET is a promising candidate for ultra‐low power applications. The subthreshold swing obtained using superposition approximation is more optimized than that of parabolic approximation technique.

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“…reported by the International Technology Roadmap for Semiconductors (ITRS) [10]. This low on-state current leads to a large switching delay (CV DD /I ON ), and therefore, practical application of the silicon TFET is hindered.…”

Section: Introductionmentioning

confidence: 99%

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Yang

et al. 2020

IEEE Access

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A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works. INDEX TERMS Tunnel field-effect transistor, band-to-band tunneling, InAs/Si heterojunction, complementary TFET inverters.

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Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

Cited by 24 publications

References 28 publications

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

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