Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Lv, Hongliang; Lu, Bin; Zhang, Yuming; Zhang, Yimen; Lv, Zhijun

doi:10.3390/nano9020181

Cited by 12 publications

(5 citation statements)

References 27 publications

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“…It is observed that the optimum value of source pocket length is 6nm. The increasing trend of ON current and decreasing trend OFF current with respect to pocket length is in agreement with the previously reported in [40]. Note that ON and OFF state current are calculated from V-I charteristics (VGS= VDS =1V for ON current and VGS= 0V, VDS =1V for OFF state current) for different TFET stractures.…”

Section: Impact Of Variation In Pocket Parameterssupporting

confidence: 90%

Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs

Kavi,

Tripathi,

Mishra

et al. 2023

Silicon

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In this article, a physics-based 2-D analytical model for electrical charateristics such as electric field, surface potential and drain current of source pocket hetero-dielectric double-gate tunnel FET (SP-HD-DG-TFET) is proposed to simultaneously increase the drain current and immune the subthreshold swing (SS). The presented structure of the device consist of source pocket of a highly n+ doped Silicon with a horizontally stacked gate-oxide structure of HfO2/SiO2. Poisson's equation has been discussed in the channel region by applying the parabolic approximation technique and appropriate boundary conditions. The expression of electric field has been developed using the channel potential model. Analytically integration of band-to-band tunneling generation rate over the channel thickness yields the drain current expression. The device's performances of SP-HD-DG-TFETs using the suggested model have been found better in terms of V-I characteristics, ION/IOFF, and SS as compared with hetero-diegetic double gate TFET (HD-DG-TFET), high-k TFET and conventional DG-TFET. The suggested model's output has been compared to simulation results produced by the SILVACO ATLAS TCAD tool and found to be good accordance between them.

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Section: Impact Of Variation In Pocket Parameterssupporting

confidence: 90%

Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs

Kavi,

Tripathi,

Mishra

et al. 2023

Silicon

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“…Sub-thermionic subthreshold swing provided by nanoscale-tunnel field-effect transistors (TFETs) enables a decrease in power supply voltage, which is a prerequisite in ultralow power applications, such as the internet of things (IoT) [ 1 , 2 ]. In the last decade, the great progress experienced in nanomaterials science have given an additional asset and new impulses to TFETs technology, which can play a leading role in the extension of Moore’s Law that converges to its end [ 2 , 3 , 4 , 5 ]. In the ultrascaled regime, the accuracy of nanofabrication is crucial for the reliability of elementary nanoelectronic nanodevices, as it can affect the performance of electronic circuits and systems [ 2 , 3 , 4 , 5 , 6 ].…”

Section: Introductionmentioning

confidence: 99%

“…In the last decade, the great progress experienced in nanomaterials science have given an additional asset and new impulses to TFETs technology, which can play a leading role in the extension of Moore’s Law that converges to its end [ 2 , 3 , 4 , 5 ]. In the ultrascaled regime, the accuracy of nanofabrication is crucial for the reliability of elementary nanoelectronic nanodevices, as it can affect the performance of electronic circuits and systems [ 2 , 3 , 4 , 5 , 6 ]. In this context, the junctionless paradigm has shown its efficiency in simplifying the elaboration of ultrascaled FETs on the one hand and in improving their performance on the other hand [ 6 , 7 , 8 , 9 ].…”

Section: Introductionmentioning

confidence: 99%

Synergy of Electrostatic and Chemical Doping to Improve the Performance of Junctionless Carbon Nanotube Tunneling Field-Effect Transistors: Ultrascaling, Energy-Efficiency, and High Switching Performance

et al. 2022

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The low on-current and direct source-to-drain tunneling (DSDT) issues are the main drawbacks in the ultrascaled tunneling field-effect transistors based on carbon nanotube and ribbons. In this article, the performance of nanoscale junctionless carbon nanotube tunneling field-effect transistors (JL CNTTFETs) is greatly improved by using the synergy of electrostatic and chemical doping engineering. The computational investigation is conducted via a quantum simulation approach, which solves self-consistently the Poisson equation and the non-equilibrium Green’s function (NEGF) formalism in the ballistic limit. The proposed high-performance JL CNTTFET is endowed with a particular doping approach in the aim of shrinking the band-to-band tunneling (BTBT) window and dilating the direct source-to-drain tunneling window, while keeping the junctionless paradigm. The obtained improvements include the on-current, off-current, ambipolar behavior, leakage current, I60 metric, subthreshold swing, current ratio, intrinsic delay, and power-delay product. The scaling capability of the proposed design was also assessed, where greatly improved switching performance and sub-thermionic subthreshold swing were recorded by using JL CNTTFET with 5 nm gate length. Moreover, a ferroelectric-based gating approach was employed for more enhancements, where further improvements in terms of switching performance were recorded. The obtained results and the conducted quantum transport analyses indicate that the proposed improvement approach can be followed to improve similar cutting-edge ultrascaled junctionless tunnel field-effect transistors based on emerging atomically thin nanomaterials.

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“…TFETs based on the band-to-band tunneling (BTBT) mechanism can break the 60 mV/decade thermal limitation of the subthreshold swing (SS) and offer steep switching under further scaled supply voltage (V DD ), becoming promising for future low power applications [1]- [4]. TFETs have been intensively investigated in recent years and are expected to be seen in semiconductor products after 2022 [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Yang

et al. 2020

IEEE Access

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A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works. INDEX TERMS Tunnel field-effect transistor, band-to-band tunneling, InAs/Si heterojunction, complementary TFET inverters.

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Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Cited by 12 publications

References 27 publications

Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs

Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs

Synergy of Electrostatic and Chemical Doping to Improve the Performance of Junctionless Carbon Nanotube Tunneling Field-Effect Transistors: Ultrascaling, Energy-Efficiency, and High Switching Performance

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

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