A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Abstract

A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works. INDEX TERMS Tunnel field-effect transistor, band-to-band tunneling, InAs/Si heterojunction, complementary TFET inverters.

A high performance trench gate tunneling field effect transistor based on quasi-broken gap energy band alignment heterojunction

“…Even for dielectrics as Al 2 O 3 , which the dielectric constant is several times lower than HfO 2 and TiO 2 , the I on drop is not exceed 43%. Generally, TFET shows high sensitivity to gate dielectric thickness and material [32,33]. But QB-TFET is not very sensitive to gate dielectric.…”

“…Tunneling field-effect transistor (TFET) is a promising candidate for low power applications [1][2][3][4][5]. The small subthreshold swing (SS) of TFET makes it possible to work in a low operating voltage.…”

Line-Tunneling iTFET with Overlapping Gate-on-Source and Drain Schottky Contact and SiGe-Pocket for Steep Subthreshold Swing and High ON-Current

“…Although many improvement methods have been proposed [8]- [12], TFET was not listed as one of the mainstream technologies in the 2018 IRDS [13] mainly due to the challenges in achieving high current, high switching speed, and high reliability. To address these issues, several TFET designs have been proposed in recent years, including Planar InAs / Si TFET [14], SOI DG TFET [15], DG Ge Pocket TFET [16], Homo-stacked L-shape TFET [17], and Line Tunnel FET [18]. However, the fabrication complexity of these various TFETs makes them impractical for implementation in useful integrated circuits.…”

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

“…Shizheng Yang et al 30 introduced an innovative InAs/Si heterojunction TFET and conducted a comprehensive analysis of various device parameters. The proposed device allows for adjustment of the effective tunneling area and current, enabling greater flexibility in TFET-based circuit design to meet specific requirements.…”