Double-gate junctionless transistor model including short-channel effects

Abstract

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V TH ), subthreshold slope (S) and drain induced barrier lowering.

Drain current model for short-channel triple gate junctionless nanowire transistors

“…This method has already been used for short channel 2G JNTs [24] and aims to describe the fact that the effective potential that reaches the source, gate and drain in short channel transistors is higher than in longer ones. The increase of the minimum potential in short channel devices is expressed by calculating an effective gate voltage (V GS,eff = V GS + φ min ) and the drain current is calculated by…”

“…The expression to calculate the saturation drain voltage for long channel transistors (V GT ) is not valid to short channel devices, because they saturate earlier due to higher lateral electric field, responsible for accelerating the carriers, which reach the saturation velocity before V GT , leading the drain current to saturate at lower values of V DS . For JNTs with L b 300 nm the following semi-empirical expression was obtained after multiple simulations [24]:…”

“…1.b and c), considering an unified expression to the charge density, leading to a single expression for the drain current continuous in all operation regimes. The proposed model is based on a previous one first developed in [21] for long channel 2G JNT, with proper adjust in the device electrostatics to accomplish the effects of the top gate while moving to a 3G structure and then including short channel effects (SCE) [24]. The approach of correcting the electrostatics to adapt the 2G JNT model to describe 3G JNTs has been first presented in [25], where the expression for the drain current is presented only for long channel transistors.…”

Semianalytical modeling of the depletion layers and their effects on the threshold voltage of a junctionless double‐gate MOSFET including trapped charges

“…Using the long‐channel approximation, analytical models including charge‐based potential, full range current model, variation of the threshold voltage caused by random dopant fluctuations, and technological constrains and design limitations have been investigated and developed for JL MOSFETs. Also, using the minimum central potential, the threshold voltage shift and the subthreshold slope for symmetric JL MOSFETs working in depletion and accumulation conditions have been determined and compared with the experimental results …”

Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

“…Moreover, by reducing the contacts' separating region, it is possible to get higher ON-OFF switching performance. Despite that several experimental and numerical studies published recently have shown the superior fabrication process properties provided by the junctionless device in comparison with the conventional one [4][5][6], the junctionless structure is more vulnerable to the impact of the source/drain parasitic resistance compared to an inversion mode structure [7,8]. The high series resistance associated to the source and drain regions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance.…”