To suppress the short‐channel effects (SCEs) and the OFF‐state current (IOFF) and increasing the ON‐state current (ION)/IOFF ratio, the conventional dual‐material double‐gate (DG) junctionless (JL) metaloxide‐semiconductor field effect transistor (MOSFET) is improved by employing the laterally graded channel doping profile and embedding a low‐doped buried layer along the center of the channel. The channel is divided into two regions under the gates and the region near the drain has higher doping level, while the buried layer has lower doping concentration than the channel. The characteristics of the proposed device are modeled analytically, simulated and compared with those of the dual‐material DGJL MOSFETs with uniformly doped and laterally graded doped channels without the buried layer. The results show that because of using the dual‐material gate, the graded doped channel, and the buried layer, the proposed DGJL MOSFET exhibits more improved performance against the SCEs and lower IOFF. The higher electric field near the source and higher carrier velocity along the channel improve the ION and the ION/IOFF ratio of the proposed device, considerably. Also, because of lower subthreshold slope, drain‐induced barrier lowering, and gate capacitance, the proposed device exhibits better switching performance than the other considered structures.

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This paper considers the depletion regions at the source and drain sides in a symmetric junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with trapped charges working in subthreshold condition. The effects of depletion layers on the potential, threshold voltage, drain‐induced barrier lowering (DIBL), and the current of the device have been investigated. The channel of the transistor is divided into 4 regions: 2 regions without and with trapped charges and 2 depletion regions on either side of the channel. Solving the 2‐dimensional Poisson's equation, a semianalytical model for the potential is achieved in these regions and the threshold voltage, the DIBL, and the current are calculated. Also, the depletion widths are calculated during the modeling and their variation against the positive and negative trapped charges is investigated. To show the importance of the depletion layers, another junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor without depletion layers is considered and the mentioned electrical properties of the 2 devices are compared with each other. Smaller central potential, threshold voltage, and current and higher DIBL are achieved when the depletion layers are considered. Good agreement between the results of the proposed model and the simulated results by TCAD software shows the physical validity of the proposed model.