Modeling of Fringing Capacitances of Ion-Implanted Double-Gate Junctionless FETs Using Conformal Mapping

Hashemi, Seyed Amir Hossein; Beigi, Kobra; Jit, Satyabrata

doi:10.1109/ted.2019.2937205

Cited by 6 publications

(1 citation statement)

References 28 publications

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“…In order to improve the performance of JLT various device structures have been reported in the literature. The JLT structures include, double-gate (DG) junctionless FETs [53], junctionless DGMOSFET with symmetrical side gates [54], tri-gate JLT [55], dielectric pocket DG junctionless FET [56,57] and DG junctionless FETs with a vertical gaussian-like doping profile [58]. However, the variability and the scalability study on single gate JLT considering the impact of substrate doping has not been studied.…”

Section: Introductionmentioning

confidence: 99%

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

Patil

2020

Eng. Res. Express

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In this work two dimensional sentaurus simulations are used to study the impact of substrate doping on scalability and the variability of the bulk planar junctionless transistor (BPJLT). The results shows that, although increasing substrate doping density in BPJLT reduces the off-state current, subthreshold slope and the drain induced barrier lowering, the on-state current of the device is almost constant. To improve digital logic circuit performance of nanoscale BPJLT, novel δ-layer BPJLT (δ-BPJLT) is being proposed by incorporating p-type δlayer below the uniformly doped device layer containing source, channel and the drain regions of BPJLT. It has been found that, the δ-layer below the device layer leads to reduction in the off-state current, process induced variability and the short-channel effects of the BPJLT. This is mainly because of the screening effect due to δ-layer under the device layer which significantly reduces the variations induced because of random dopant fluctuations.

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