Doping Incorporation in InAs nanowires characterized by capacitance measurements

Abstract

Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the threshold voltages of nanowire capacitors with different diameter are determined and analyzed using an improved radial metal-insulator-semiconductor field-effect transistor model. This allows for a separation of doping in the core of the nanowire from the surface charge at the side facets of the nanowire. The data show that the doping level in the InAs nanowire can be controlled on the level between 2×1018 to 1×1019 cm−3, while the surface charge density exceeds 5×1012 cm−2 and is shown to increase with higher dopant precursor molar fraction.

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

“…The method used in the here presented implementation, that is uniform doping of the transistor channel, needs further refinement beyond diameter scaling in order to avoid increase in the access resistance. Increased doping control may be one alternative to reduce the source/drain resistance [9]. Alternatively, the access regions may be regrown, although at the cost of parasitic capacitance [10].…”

“…The Si is highly resistive and the InAs layer is grown without intentional doping (n = 3·10 18 cm -3 ) demonstrating a sheet resistance of 36 Ω/□. Definition of size and position of gold seed particles is made with electron-beam-lithography and growth of InAs nanowires is performed in an metal-organicvapor-phase-epitaxy (MOVPE) growth chamber at 420 °C and with a Sn dopant flow corresponding to a doping level of ~1·10 18 cm -3 [9]. For a-FETs, NWs are placed in zigzag rows to reduce the parasitic capacitance within the array [10], with 300 nm spacing between each NW (see Fig.…”

Effect of Si-doping on InAs nanowire transport and morphology

“…At large negative gate voltages no complete pinchoff of the drain current was achieved, possibly caused by a by-pass channel due to an accumulation layer at the nanowire surface. 31 The electron concentration in the nanowire can be estimated from the threshold voltage, V th , i.e., the gate voltage where the drain current is pinched off. Since in our case no complete suppression of I D was achieved, V th was extracted by extrapolation [cf., Figure 7, (left inset)].…”

“…However, it has to be kept in mind that the doping of nanostructures may not only change the carrier concentration but also the morphology. Up to now, successful n-or p-type doping has already been reported for various III-V semiconductor nanowires, such as InAs, 7,[30][31][32] GaAs, 33,34 or InN nanowires. 35 The doping of InAs nanowires by SA-MOVPE has not been reported, especially at the high growth temperature needed when using an N 2 ambient.…”

Surface and core contribution to 1/f-noise in InAs nanowire metal-oxide-semiconductor field-effect transistors

“…The NWs are positioned with electron beam lithography, where placement of gold-discs that assembles the material is accomplished through a lift-of process. The growth is performed at 420 C having a constant dopant flow of Sn with a molar fraction of 1.07 Â 10 À7 , corresponding to an estimated 7 doping concentration of N D $ 1 Â 10 18 cm À3 . After growth, the NWs are covered with a high-k film consisting of 0.5 nm Al 2 O 3 deposited at 250 C and 6.5 nm of HfO 2 deposited at 100 C, with the use of atomic layer deposition (ALD).…”