Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

Persson, Karl‐Magnus; Berg, Martin; Borg, Mikael; Wu, Jun; Johansson, Sofia; Svensson, Johannes; Jansson, Kristofer; Lind, Erik; Wernersson, Lars‐Erik

doi:10.1109/ted.2013.2272324

Cited by 62 publications

(50 citation statements)

References 23 publications

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“…Scalability and excellent DC characteristics have previously been shown [5], [6]. However, the RF characteristics in earlier reports, with f t = 17 GHz and f max = 30 GHz, have been suppressed by the large parasitic capacitances caused by large metal overlaps in the vertical structure [6]- [8].…”

Section: Introductionmentioning

confidence: 93%

“…sample and device isolation is postponed compared to previous reports [6], [7]. At this point, the source pad pattern is etched in the high-κ gate dielectric only.…”

Section: Device Fabricationmentioning

confidence: 99%

“…A 60-nm-thick Si 3 N 4 gate-source spacer is deposited by plasma-enhanced chemical vapor deposition (PECVD) [6]. The W gate metal is deposited by sputtering and patterned together with the source-gate spacer by a combination of UV lithography and electron beam lithography (EBL) followed by reactive ion etching (RIE) with SF 6 and Ar.…”

Section: Device Fabricationmentioning

confidence: 99%

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High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Johansson

Memišević

Wernersson

et al. 2014

IEEE Electron Device Lett.

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We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gateall-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ∼80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

show abstract

Section: Introductionmentioning

confidence: 93%

“…sample and device isolation is postponed compared to previous reports [6], [7]. At this point, the source pad pattern is etched in the high-κ gate dielectric only.…”

Section: Device Fabricationmentioning

confidence: 99%

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High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Johansson

Memišević

Wernersson

et al. 2014

IEEE Electron Device Lett.

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“…The array of nanowires in each device consists of nominally 192 nanowires. A detailed description of the device fabrication may be found elsewhere [9], [10].…”

Section: Introductionmentioning

confidence: 99%

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Johansson

Berg

Persson

et al. 2013

IEEE Trans. Electron Devices

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“…FinFET [6], instead, has become a more practical solution for scaled semiconductor technologies [7]. However, as conventional scaling hits its barriers below the regime of 10nm, vertically fabricated transistors are reconsidered to be one of the replacements of FinFET devices [8]. Recent studies on vertical devices have demonstrated the improved fabrication process control and many appealing properties [9,10].…”

Section: Introductionmentioning

confidence: 99%

Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

Wang

Gupta

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Vertical gate-all-around (VGAA) has been shown to be one of the most promising devices for the scaling beyond 10nm for its reduced delay, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and simple standard cells like inverter. Since naive migration of regular FinFET layouts to vertical FETs yields little benefits, we identify several vertical efficient layout structures and propose novel layout generation heuristics for vertical channel devices. We also compare VGAA with symmetric and asymmetric source/drain architectures. The layout efficiencies of several VGAA structures, vertical double gate (VDG), lateral gate-all-around (LGAA), and FinFET are presented in our experiments. We observe that even though most vertical channel standard cells have more diffusion gaps than lateral cells do, they still benefit from vertical architectures in area because of the elimination of diffusion contacts. For asymmetric architectures, the area is larger than symmetric architectures because of the extra diffusion gaps needed, but our experiments indicate that for both symmetric and asymmetric architectures, vertical channel devices are likely to have a density advantage over lateral channel devices assuming that current drive strengths of both are similar.

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Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

Cited by 62 publications

References 23 publications

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

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