We present a capacitance-voltage study for arrays of vertical InAs nanowires. Metal-oxide-semiconductor (MOS) capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr∕Au metallization as one of the capacitor’s electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.

Sn and Se doped InAs nanowires are characterized using a capacitance-voltage technique where the threshold voltages of nanowire capacitors with different diameter are determined and analyzed using an improved radial metal-insulator-semiconductor field-effect transistor model. This allows for a separation of doping in the core of the nanowire from the surface charge at the side facets of the nanowire. The data show that the doping level in the InAs nanowire can be controlled on the level between 2×1018 to 1×1019 cm−3, while the surface charge density exceeds 5×1012 cm−2 and is shown to increase with higher dopant precursor molar fraction.

The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a Poisson-Schrödinger solver, information about the doping density can be obtained directly. Further features in the measured capacitance-voltage characteristics can be attributed to the presence of surface states as well as the coexistence of electrons and holes in the wire. For both scenarios, quantitative estimates are provided. It is furthermore shown that the difference between the actual capacitance and the geometrical limit is quite large, and depends strongly on the nanowire material.

High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap.

Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (Dit). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al2O3 and HfO2) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO2 and Al2O3 MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (Dit) profiles show Dit minima of 6.1 × 1012/6.5 × 1012 and 6.6 × 1012/7.3 × 1012 cm−2 eV−1 for Al2O3 and HfO2, respectively for (100) and (110) InAs surfaces. The similar interface trap density (Dit) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present.

Single-shot transients and deep-level transient spectroscopy are used to investigate the origins of capacitance hysteresis in n-doped InAs nanowire/HfO2 capacitors. Capacitance transients with a characteristic time in the order of 100 μs are attributed to emission from electron traps, located in the oxide film. The trap energy is determined to be in the range from 0.12 to 0.17 eV with capture cross-sections of about 1.7×10−17 cm−2. The capture is measured to be shorter than 100 ns with no sign of capture barrier. Under the reverse bias, the transients show a reduced emission rate indicating a minority carrier assisted complex dynamics.

We demonstrate the use of a GaAs-AlGaAs gated tunnel diode (GTD) in an ultra-wideband (UWB) wavelet generator. An inductor is integrated to form an oscillator circuit, which is driven by the negative differential conductance property of a GTD. It is demonstrated that as the gate tunes the magnitude of the output conductance, the oscillator may be switched on and off, creating short RF pulses. The shortest pulses generated are 500 ps long, the highest output power for the free running oscillator is 4.1 dBm, and the highest oscillation frequency is 22 GHz. Analytical expressions based on the van der Pol equation describing the pulse length and amplitude are presented. This technique is applicable for high frequency impulse radio UWB implementations.Index Terms-Impulse radio (IR), oscillator, pulse generator, resonant tunneling transistor, ultra-wideband (UWB), wavelet generator.

No abstract