Directional bias and non-uniformity in FPGA global routing architectures

Betz, Vaughn; Rose, Jonathan

doi:10.1109/iccad.1996.571342

Cited by 44 publications

(30 citation statements)

References 8 publications

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“…We have experimented with several different cost functions, and found that what we call a linear congestion cost function provides the best results in a reasonable computation time [8]. The functional form of this cost function is where the summation is over all the nets in the circuit.…”

Section: Placement Algorithmmentioning

confidence: 99%

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VPR: a new packing, placement and routing tool for FPGA research

Betz

Rose

1997

Field-Programmable Logic and Applications

806

654

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We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.VPR is capable of targeting a broad range of FPGA architectures, and the source code is publicly available. It and the associated netlist translation / clustering tool VPACK have already been used in a number of research projects worldwide, and should be useful in many areas of FPGA architecture research.

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Section: Placement Algorithmmentioning

confidence: 99%

“…VPR's router is based on the Pathfinder negotiated congestion algorithm [14,8]. Basically, this algorithm initially routes each net by the shortest path it can find, regardless of any overuse of wiring segments or logic block pins that may result.…”

Section: Routing Algorithmmentioning

confidence: 99%

VPR: a new packing, placement and routing tool for FPGA research

Betz

Rose

1997

Field-Programmable Logic and Applications

806

654

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“…On average, signals will have to travel further in the long direction of the FPGA so channels in this direction should have a higher track capacity. This is quantified in [3]; however, [3] approaches the problem using global routing only. However, due to the limited connectivity with programmable logic routing, the detailed routing architecture will have a significant effect on the optimum channel widths for a given programmable logic core.…”

Section: Introductionmentioning

confidence: 99%

“…In [3], it was suggested that for a rectangular FPGA, channels in the long direction should have more tracks than channels in the narrow direction (as shown in Figure 2). On average, signals will have to travel further in the long direction of the FPGA so channels in this direction should have a higher track capacity.…”

Section: Introductionmentioning

confidence: 99%

Detailed routing architectures for embedded programmable logic IP cores

Hallschmid

Wilton

2001

Proceedings of the 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays

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As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.

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“…Specifically, Odin can interface with Altera's Quartus CAD flow [16], and a VPR [27] CAD flow. To attach to each of these CAD flows, first, Odin converts Verilog designs into structural Verilog netlists consisting of gate primitives and LPMs (or the equivalent of LPMs) targeted for a particular flow.…”

Section: Cad Flow and Verificationmentioning

confidence: 99%

A verilog RTL synthesis tool for heterogeneous FPGAs

Jamieson¹,

Rose²

International Conference on Field Programmable Logic and Applications, 2005.

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Modern heterogeneous FPGAs contain "hard" specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible "soft" programmable logic and routing. These hard structures provide major benefits, yet raise interesting questions in FPGA CAD and architecture. To develop high-quality CAD mapping algorithms for these structures, and indeed to measure the quality of proposed new structures in the architectural domain, it is essential to have a flexible tool at the RTL synthesis level that permits heterogeneous FPGA CAD and architecture experimentation. In this paper we present a synthesis tool, called Odin, and an algorithm that permits flexible targeting of hard structures in FPGAs. Odin maps Verilog designs to two different FPGA CAD flows: Altera's Quartus, and the academic VPR CAD flow. We have expended significant effort to make the quality of this tool comparable to an industrial front-end synthesis tool, and we present mapping results for our benchmarks that show the quality of our results.

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Directional bias and non-uniformity in FPGA global routing architectures

Abstract: Abstract

Cited by 44 publications

References 8 publications

VPR: a new packing, placement and routing tool for FPGA research

VPR: a new packing, placement and routing tool for FPGA research

Detailed routing architectures for embedded programmable logic IP cores

A verilog RTL synthesis tool for heterogeneous FPGAs

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