Digital methods of offset compensation in 90nm CMOS operational amplifiers

Nagy, Gabriel; Arbet, Daniel; Stopjaková, Viera

doi:10.1109/ddecs.2013.6549802

Cited by 6 publications

(5 citation statements)

References 2 publications

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“…Then, the mirrored compensation currents (I F C1 , I F C2 ) are injected into the respective side of the OPAMP folded cascode. Extra correction circuit and its contribution were described in details in [8].…”

Section: Opamp Offset Compensationmentioning

confidence: 99%

“…3. Detailed description of the proposed trimming process was published in [7], [8]. Since the compensation currents (I lef t and I right ) in the M-2M compensating network (Fig.…”

Section: Opamp Offset Compensationmentioning

confidence: 99%

“…Another extra hardware is the trimming block, which includes also control logic that is realized using a serial counter and converting network that generates the compensating current for the respective side of the folded cascode stage. A voltage comparator has been used to compare the OPAMP output voltage to the reference voltage and to indicate the completion of the trimming process [8]. In this case, a simple invertor was used as the voltage comparator.…”

Section: Opamp Offset Compensationmentioning

confidence: 99%

“…The DAC consists of the converter itself (yellow parts) and on-chip additional hardware necessary for the self-calibration process (blue blocks), including control logic and the trimming block. Compensation of the OPAMP input offset voltage as well as additional circuitry needed for this purpose are described in more details in [7], [8]. …”

Section: Self-calibrated Dacmentioning

confidence: 99%

See 3 more Smart Citations

A self-calibrated binary weighted DAC in 90nm CMOS technology

Arbet

Nagy

Stopjaková

et al. 2014

2014 29th International Conference on Microelectronics Proceedings - MIEL 2014

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In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error can be obtained.

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Section: Opamp Offset Compensationmentioning

confidence: 99%

“…3. Detailed description of the proposed trimming process was published in [7], [8]. Since the compensation currents (I lef t and I right ) in the M-2M compensating network (Fig.…”

Section: Opamp Offset Compensationmentioning

confidence: 99%

Section: Opamp Offset Compensationmentioning

confidence: 99%

Section: Self-calibrated Dacmentioning

confidence: 99%

See 2 more Smart Citations

A self-calibrated binary weighted DAC in 90nm CMOS technology

Arbet

Nagy

Stopjaková

et al. 2014

2014 29th International Conference on Microelectronics Proceedings - MIEL 2014

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“…Therefore, the opamps used in the read circuit or the opamps used to buffer crossbar lines should be finely calibrated to keep their DC offset voltages as low as possbile. Conventional calibration schemes exist that compensate offset ranges in the order of few mV [12], [13]. However, this is not enough to increase the required scalability in neuromorphic processors.…”

Section: Introductionmentioning

confidence: 99%

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar

Mohan

Camuñas-Mesa

Vianello

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

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