A self-calibrated binary weighted DAC in 90nm CMOS technology

Abstract

In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error can be obtained.

Low-Power CMOS Frequency Comparator

“…In order to obtain a wide voltage range of operation, a rail-to-rail input stage was used in the designed analog comparator [5]- [7]. Therefore the NMOS input differential pair M1-M2 is connected in parallel with the PMOS input pair M3-M4.…”

An embedded offset and gain instrument for OpAmp IPs

“…The exact offset value of an OpAmp IP can be measured by unit-gain feedback-loop method [3] or calibration source methods [4]. These methods are either configuring the OpAmp into a unit-gain feedback system or applying extra calibration sources to the OpAmp and comparing its output.…”

“…If the loop gain V in •K •G approaches −1, V c will be driven to positive infinity or negative infinity, depending on which direction the loop gain approaches −1. For example, if K is larger than K spc , it can be expressed as (4).…”