Digital Integrated Circuits on an E-Mode GaN Power HEMT Platform

Tang, Gaofei; Kwan, Alex Man Ho; Wong, Roy K.-Y.; Lei, Jiacheng; Su, R.Y.; Yao, F.-W.; Lin, Yo-Sheng; Yu, Jingshu; Tsai, Tom; Tuan, H.C.; Kalnitsky, Alexander; Chen, Kevin J.

doi:10.1109/led.2017.2725908

Cited by 81 publications

(42 citation statements)

References 15 publications

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“…The width of the transition voltage region (VTR= VIH -VIL) is a way of measure the ambiguity of the logic inverter [14], which must be as low as possible. The transition voltage width was 0.6 V/5 V (12%) in our case, which is smaller than the lowest values in the literature 1 V/5 V (20%) [10] and 1.6 V/7 V (22%) [13]. The low-input-logic noise margin (NML=VIL -VOL) and high-inputlogic noise margin (NMH=VIH -VOH) are 2.13 V/ 2.5V (85.2%) and 2.2 V/2.5 V (88%) respectively, which outperforms the best values of 1.7 V/2.5 V (68%) and 2 V/2.5 V (80%) in [10].…”

Section: Resultscontrasting

confidence: 80%

“…The voltage swing at 300 °C was 4.85 V/5 V (97%), with 1.6% degradation compared with the value at RT. This value is much larger than the best values in the literatures 4.5 V/5 V (90%) in [10] at 200°C and 6.5 V/7 V (93%) in [11] at 300°C. NML and NMH at 300°C were 1.85 V/2.5 V (74%) and 2.1 V/2.5V (84%), respectively, which shows an excellent operation even at 300°C.…”

Section: Resultscontrasting

confidence: 60%

“…54. The high-level output voltage (VOH) and VOL were 5 V and 0.07 V, respectively, yielding a much larger voltage swing of 4.93 V/5 V (98.6%) compared to the best values in the literature of 4.66 V/5 V (93.2%) [10] and 6.3 V/7 V (90%) [13]. The low-level input voltage (VIL) and high-level input voltage (VIH), defined at dVout/dVin = -1, were 2.2 V and 2.8 V respectively.…”

Section: Resultsmentioning

confidence: 79%

“…GaN DCFLs have been demonstrated [9]- [12], however their performances are not sufficient to satisfy the logic requirements, due to their small noise margins, large logic transition voltages, small logic swing and large low-level output voltages (V OL). Recent research show steady improvements on GaN DCFL [10], however the VOL is still quite high, up to 0.3 V and the maximum voltage swing is 4.66 V, which would lead to high logic losses and safety problems. A very distinct property of GaN compared to Silicon is its high temperature operation, which led to the demonstration of GaN DCFLs operating at high temperatures, up to 375 °C [9], [11], however, it resulted in a much degraded operation compared to room temperature (RT).…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu

Matioli

2018

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300°C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and highoutput noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.

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Section: Resultscontrasting

confidence: 80%

Section: Resultscontrasting

confidence: 60%

Section: Resultsmentioning

confidence: 79%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu

Matioli

2018

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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“…GaN high electron mobility transistors (HEMTs) are used in high frequency, high power, and robust low-noise applications [1][2][3]. Linearity is one of the most crucial figures of merit for the application of power amplifiers.…”

Section: Introductionmentioning

confidence: 99%

Numerical Optimization for Source-Drain Channel Resistance of AlGaN/GaN HEMTS

Yahyazadeh

Hashempour

2019

JST

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A numerical model for the source-drain channel resistance based high electron mobility transistors has been developed that is capable to predict accurately the effects of polarization Coulomb Field Scattering (PCF), multi sub-band on source-drain channel resistance. Salient features of the model are incorporated of fully and partially occupied sub-bands in the interface quantum well, combined with a self-consistent solution of the Schrödinger and Poisson equations. In addition, to develop the model, accurate two-dimensional electron gas mobility and modified wave function in barrier AlGaN have been used. According to the numerical calculations, the effect of multi sub-band and PCF scattering on the increase of source-drain channel resistance is 35% and 65%, respectively, with the effect of PCF being almost twice as high as multi sub-band. The calculated model results are in very good agreement with existing experimental data for high electron mobility transistors device.

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Monolithic n‐Type Metal–Oxide–Semiconductor Inverter Integrated Circuits Based on Wide and Ultrawide Bandgap Semiconductors

Chettri,

Mainali,

Xiao

et al. 2024

Physica Status Solidi (b)

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Wide bandgap (WBG) and ultrawide bandgap (UWBG) semiconductors in n‐type metal–oxide–semiconductor (n‐MOS) integrated circuits (ICs) are increasingly being explored for their potential applications in the rapidly developing field of electronics. This review comprehensively examines the role of n‐MOS inverters underpinned by WBG and UWBG semiconductors and their application possibilities. It delves into various n‐MOS inverter topologies, including resistive, enhancement or diode‐load, depletion‐load, and pseudo‐complementary MOS inverter topologies. Each topology's operational principles, unique advantages, and potential performance are elucidated in detail. Finally, these topologies are simulated using the Advanced Design System software for a fair comparison between various topologies. The literature and simulation results show that the pseudo‐D topology has the best gain and improved noise margin. The review methodology involves an extensive exploration of WBG/UWBG n‐MOS inverters to advance the current understanding of WBG/UWBG n‐MOS‐based ICs.

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Digital Integrated Circuits on an E-Mode GaN Power HEMT Platform

Cited by 81 publications

References 15 publications

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Numerical Optimization for Source-Drain Channel Resistance of AlGaN/GaN HEMTS

Monolithic n‐Type Metal–Oxide–Semiconductor Inverter Integrated Circuits Based on Wide and Ultrawide Bandgap Semiconductors

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