Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu, Minghua; Matioli, Elison

doi:10.1109/ispsd.2018.8393646

Cited by 35 publications

(25 citation statements)

References 11 publications

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“…Some methods based on D-mode GaN technology, for example, gate recess process [6][7][8] and F ion implantation [9,10] have been proposed to realize E-mode GaN high-electronmobility transistors (HEMTs) and E/D-mode inverters. These works are either based on Schottky-gate HEMTs or MIS (metal-insulated-semiconductor)-gate HEMTs, and neither of them have been adopted in commercial GaN power devices, due to small gate swing in Schottky-gate HEMTs and gate-dielectric reliability concerns in MIS-HEMTs.…”

Section: Introductionmentioning

confidence: 99%

E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Jia

Lian

Xiao³

et al. 2021

Micromachines

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AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.

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Section: Introductionmentioning

confidence: 99%

E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Jia

Lian

Xiao³

et al. 2021

Micromachines

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“…Hence, co-integrating Si with GaN on a single chip may help in achieving high power and high-performance application. The main motivation for integrating GaN and CMOS is due to the superior GaN performance in fast power switching and the high functionality of CMOS logic, reduction in interconnect distance as well as losses, smaller form factor, reduction in power consumption, lower cost, and lower assembling complexity [191,192]. There are two types of GaN and CMOS integration variants on wafer-level namely Monolithic Integration and Heterogeneous Integration (HI).…”

Section: Heterogeneous Integration Of Gan Hemtmentioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

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“…a half bridge [9], [10]. With the integration of enhancement and depletion mode transistors NAND, NOR or NOT logic patterns can be built [11]. Just by design, mainly the gate to drain drift region spacing, transistors with different voltage rating can be realized e.g.…”

Section: Monolithic Integration In Ganmentioning

confidence: 99%

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Lerner¹,

Hansen²

2021

ISPS'21 Proceedings

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Several approaches for close integration of power switches with CMOS logic are subject of technical evaluations and academic discussions. This paper identifies the commercially relevant processing steps of different integration methods (HV and SOI CMOS, monolithic integration in SOI and in GaN, Direct Wafer Bonding, micro-Transfer-Printing of GaN on CMOS and CMOS on GaN) and compares them on simple cost per wafer and cost per chip models. Four examples of real ICs verify the simple costs per chip model. Commercially attractive high voltage to logic partitionings are identified for the different integration approaches.

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Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Cited by 35 publications

References 11 publications

E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

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