Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

Li, Jin-Fu; Tzeng, Ruey-Shing; Wu, Cheng‐Wen; Chakrabarty, Krishnendu

doi:10.1007/978-1-4757-6527-4_10

Cited by 4 publications

(5 citation statements)

References 10 publications

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“…In the weak inversion, the diffusion current occurs in the subthreshold conduction when the minority carriers are conducted from channel region and exist in channel depletion layer. This subthreshold current can be expressed as follows [24]: (10) where (11) where is the threshold voltage; is the thermal voltage, is temperature;…”

Section: A Leakage Mechanismsmentioning

confidence: 99%

Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

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The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

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Section: A Leakage Mechanismsmentioning

confidence: 99%

Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

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“…Test data compression methods can reduce the volume of test data applied to the core under test (CUT) or the volume of test responses sent to the ATE. Test response compression is carried out using signature analyzers [18], however, if diagnosis is necessary special schemes may be required [19,20]. In this paper, we will focus on the former due to the large volumes of test data required to test logic cores, assuming signature analyzers to compress the test output responses.…”

Section: Existing Approaches To Reduce Volume Of Test Datamentioning

confidence: 99%

Variable-length input huffman coding for system-on-a-chip test

Gonciari

Al-Hashimi

Nicolici

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

146

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This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new Variable-length Input Huffman Coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, whencompared to three previous approaches [1][2][3], which reduce some test data compression environment's parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.

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“…The address difference between the word under test (WUT) and the last faulty word, d, is represented using the address levels as shown in Table 1. The Compressed Syndrome is obtained from compressing the Word Syndrome by Huffman Code [7]. However campared with the conventional fault syndrome, the size of the proposed fault syndrome, and thus the data export time, can be reduced.…”

Section: %mentioning

confidence: 99%

“…Proper identification of the fail patterns, however, is not trivial. A faultsyndrome compression method based on a Huffman-like compression scheme is proposed in [7]. The Huffmanlike approach improves the compression ratio, and its hardware overhead is low.…”

Section: Introductionmentioning

confidence: 99%

Embedded memory diagnostic data compression using differential address

Huang

et al.

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

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Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester, The cost of the diagnosis process highly depends on the data volumn sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volumn. Experimental results show that the BISD design is cost-effective. AddressWord SyndromeConveotional Differential ID Session Differentid Address Compresscd Syndrome

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Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

Cited by 4 publications

References 10 publications

Testing Methodology of Embedded DRAMs

Testing Methodology of Embedded DRAMs

Variable-length input huffman coding for system-on-a-chip test

Embedded memory diagnostic data compression using differential address

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