Development of High-Quality Gate Oxide on 4H-SiC Using Atomic Layer Deposition

Abstract

A systematic post-deposition annealing study on Silicon Carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) using atomic layer deposition (ALD)-deposited silicon dioxide (SiO2) layers was carried out. Anneals were done in oxidising (N2O), inert (Ar) and reducing (H2:N2) ambients at elevated temperatures from 900°C to 1300°C for 1 hour. Electrical characterisation results show that the forming gas treatment at 1100°C reduces the flatband voltage to 0.23 V from 10 V for as-deposited SiO2 layers. The density of interface traps (DIT) was also reduced by one order of magnitude to 2×1011 cm-2 eV-1 at EC-ET = 0.2 eV. As an indicator of the improvement, characterisation by x-ray photoelectron spectroscopy (XPS) showed that silicon enrichment present in as-deposited layers was largely reduced by the forming gas anneal, improving the stoichiometry. Time-dependent dielectric breakdown (TDDB) results showed that the majority of forming gas annealed samples broke down at breakdown fields of 12.5 MV × cm-1, which is about 2.5 MV × cm-1 higher than for thermally oxidised samples.

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

“…Oxides formed using ALD and thermal oxidation were considered. A FG postdeposition anneal was carried out on ALD-deposited samples since this process has recently shown a big improvement in terms of electrical parameters and interface quality when compared to as-deposited ALD silicon dioxide and thermal oxide [16,17].…”

“…Following deposition, one set of samples (freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC) was left as-deposited, and a second set of samples was loaded into a high-temperature anneal furnace, where they were annealed in forming gas (FG, 5% H 2 in 95% N 2 ) for 1 h with a gas flow of 5 slm and a temperature of 1100 • C, as this process has been reported to improve the interface on 4H-SiC/SiO 2 MOSCAPs [16].…”

(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

“…Also, Figure 2 shows (a) a typical set of C-V responses as well as (b) density of interface trap, DIT, levels, which were plotted over the trap energy level position, ET, below the conduction band edge, EC. All the investigated MOSCAPs had flatband voltage values close to zero, with the ALD-deposited oxide showing the lowest level, averaging 0.63 V. For benchmarking, the electric performance of ALD as-deposited SiO2 layers has been published by the authors before and can be found in [5,7], where the asdeposited layers showed average flatband voltage values of >8 V. Here, the ALD-deposited oxide that subsequently underwent a PDA in N2O ambient also had a very tight distribution of hysteresis voltages and frequency dispersions, which averaged at 0.28 V and 0.11 %.dec -1 respectively. The LPCVD-deposited and thermally grown oxide layers only show marginal flatband voltage deviations from the ALD-deposited layers, averaging 1.13 V and 0.96 V respectively.…”

High Mobility Silicon Dioxide Layers on 4H-SiC Deposited by Means of Atomic Layer Deposition

“…They also do not consume any of the SiC material, meaning that the interface is less likely to be carbon-rich after deposition [3]. However, the electrical properties of as-deposited SiO2 layers are poor [3,4], and, after their deposition on SiC, a post-deposition anneal (PDA) typically follows in a nitrogen-containing ambient, such as nitric (NO) or nitrous oxide (N2O) at temperatures above 1,100°C [5]. In this work, we present the improvement brought about by deploying ALD-deposited SiO2 layers which were post-deposition annealed in forming gas (FG) and N2O ambient.…”