(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

Abstract

An investigation into the effect of deposition, growth and conditioning of the SiO2/SiC interface in MOS capacitors is performed, where the enhancement of reliability is characterised. Various methods of oxide formation are compared: ALD, LPCVD and thermally grown. ALD-deposited oxides were post-deposition annealed in nitrous oxide ambient, resulting in average flatband voltages of 0.63 V and low D IT levels, down to 7 x 1011 cm-2 eV-1 at EC-ET =0.2 eV. These samples also outperformed their counterparts in terms of high leakage and constant voltage TDDB performance, which was done at 175°C, averaging breakdown electric fields of 9.84 MV/cm and a 63% failure stress time of 11220 s when stressed at 8 MV/cm.

High Mobility Silicon Dioxide Layers on 4H-SiC Deposited by Means of Atomic Layer Deposition

“…Room temperature vertical C-V measurements were performed on at least 20 MOSCAPs using an Agilent E4980A LCR meter to extract flatband voltage, hysteresis and frequency dispersion values, which are not going to be separately reported here. The results of these measurements can be found in [6]. Furthermore, vertical I-V as well as constant-voltage TDDB measurements were performed at 175°C using a Semiprobe semi-automatic probe station with a Keysight B1505A parameter analyser.…”