Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

Abstract

This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 µm width and 450 nm depth) with a density of 1.09 × 10 5 cm −2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C-V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3 × 10 11 cm −2 eV −1 at E C −E T = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.

Al2O3 Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices

“…in the order of 2 × 10 12 cm −2 eV −1 [8]. On the other hand, the PE-Al2O3/SiO2/3C-SiC sample showed a lower Dit distribution close to the 3C-SiC conduction band edge in the order of 5 × 10 11 cm −2 eV −1 , which can be due to the beneficial effect of the O2-plasma on the defects amount at SiO2/SiC interface [40].…”

“…The cubic polytype of silicon carbide (3C-SiC) has a smaller energy gap (E g = 2.36 eV) [ 1 , 2 ] compared to the hexagonal 4H-SiC (E g = 3.26 eV) [ 3 ], but it possesses a higher electron mobility and saturation velocity [ 4 , 5 , 6 , 7 , 8 ]. Moreover, it exhibits a larger conduction band offset (3.7 eV) [ 9 ] with SiO 2 than 4H-SiC (2.7 eV).…”

“…Silicon dioxide (SiO 2 ) is the native oxide of SiC that can be obtained by a thermal oxidation process of the material [ 13 , 14 ]. However, its electrical behavior is adversely affected by the large number of defects [ 9 , 15 ] (e.g., carbon clusters and dangling bonds produced during oxidation), which results in a large negative shift of the flat band voltage (V FB ) [ 8 , 16 , 17 ]. Another issue is the response of the MOS system to the application of high voltages.…”

Nanostructured 3C-SiC on Si by a network of (111) platelets: a fully textured film generated by intrinsic growth anisotropy

“…The cubic phase of SiC (3C-SiC) has been extensively investigated in the last few years as an alternative candidate to wurtzite GaN for power devices in the medium range of 600-1200 V. 1 In addition to the good mobility of carriers, cubic SiC grows on cheap Si (001) or Si (111) substrates, which is surely advantageous with respect to the homoepitaxial growth of the hexagonal 4H-SiC on expensive substrates. 2,3 However, the presence of multiple stacking faults (SFs) and anti-phase boundaries (APBs) is still hindering the realization of efficient power devices. 4,5,6 In particular, SFs are present at the surface of a film, as thick as some tens of µm, at a linear density of several 10 3 cm -1 : despite that the leakage of current in reverse bias appears to be larger in the case of APBs, 7 such a density is still one order of magnitude larger than that required for device manufacturing.…”

High channel mobility of 3C-SiC n-MOSFETs with gate stacks formed at low temperature—the importance of Coulomb scattering suppression

“…MOSFET #1 shows a negatively shifted threshold voltage (V TH ), which agrees with the former studies on MOS capacitors and MOSFETs with thermally oxidized gate insulators. 15,18,19) The negative shift of V TH is caused by a large amount of positive fixed charges in the thermally oxidized gate insulator. This insulator covers not only the channel but also most of the surface of the 3C-SiC (except for the Al electrodes of S/D).…”