Development, characterisation and simulation of wafer bonded Si-on-SiC substrates

Gammon, P. M.; Chan, C.W.; Li, F.; Gity, Farzan; Trajković, T.; Pathirana, V.; Flandre, Denis; Kilchytska, Valeriya

doi:10.1016/j.mssp.2017.10.020

Cited by 13 publications

(8 citation statements)

References 13 publications

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“…According to previous experimental results [20, 21], the Si/SiC interfacial charges are introduced during the direct bonding process. In the simulation, the influence of acceptor‐like traps at the Si/SiC interface is investigated in Fig.…”

Section: Resultsmentioning

confidence: 99%

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Duan

Xing

Yang

2019

Micro & Nano Letters

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A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance (R on,sp). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figureof-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

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Section: Resultsmentioning

confidence: 99%

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Duan

Xing

Yang

2019

Micro & Nano Letters

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“…The surface of SiC wafer and SOI wafer are both RCA cleaned. Then, bond the SiC and SOI wafer with the method in [17]. The SOI wafer is thinned by CMP, before a HF solution is used to remove the buried oxide.…”

Section: Device Structure and Descriptionmentioning

confidence: 99%

“…Therefore, in recent years, the Si/SiC substrates are mostly fabricated by wafer bonding process. In 2018, P.M. Gammon et al proposed a method of producing Si/SiC substrates by wafer bonding silicon-oninsulator (SOI) wafers to 4H-SiC [ 17 ]. This method can effectively improve the Si/SiC interface quality problem caused by lattice-misfit.…”

Section: Introductionmentioning

confidence: 99%

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

Duan

Xue

Huang

et al. 2021

IEEE J. Electron Devices Soc.

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A novel Si/SiC heterojunction Lateral Doublediffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The RON,SP of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ•cm 2 of Cov. LDMOS to 24.0mΩ•cm 2 , decreased by 27.7%. Furthermore, the figure-of-merit (FOM=BV 2 /Ron,sp) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm 2 , which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

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“…SiC films also serve as the host matrix in three exciting new areas of technical innovation. In power electronics, SiC enables the fabrication of high-voltage, high-current devices that can be operated at elevated temperatures [6][7][8]; SiC is also increasingly used in micro-electro-mechanical-systems (MEMS) due to its higher thermal conductivity, higher voltage power, and higher breakdown voltage compared to Si [3]; In nanophotonics, quantum and nonlinear photonics technologies exploit a wide array of SiC properties, including high refractive index, strong second-and third-order optical nonlinearity, and a broad ultra-violet-to-mid-infrared transparency window [9][10][11][12]. For these reasons, SiC also acts as a base platform for a number of optically addressable spin qubits [13].…”

Section: Introductionmentioning

confidence: 99%

Defect- and H-Free Stoichiometric Silicon Carbide by Thermal CVD from the Single Source Precursor Trisilacyclohexane

Kaloyeros¹,

Goff

Arkles

2022

Electronic Materials

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Stoichiometric silicon carbide (SiC) thin films were grown using thermal chemical vapor deposition (TCVD) from the single source precursor 1,3,5-trisilacyclohexane (TSCH) on c-Si (100) substrates within an optimized substrate temperature window ranging from 650 to 850 °C. X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared spectroscopy (FTIR) analyses revealed that the as-deposited films consisted of a Si-C matrix with a Si:C ratio of ~1:1. FTIR and photoluminescence (PL) spectrometry studies showed that films deposited ≥ 750 °C were defect- and H-free within the detection limit of the techniques used, while ellipsometry measurements yielded an as-grown SiC average refractive index of ~2.7, consistent with the reference value for the 3C-SiC phase. The exceptional quality of the films appears sufficient to overcome limitations associated with structural defects ranging from failure in high voltage, high temperature electronics to 2-D film growth. TSCH, a liquid at room temperature with good structural stability during transport and handling as well as high vapor pressure (~10 torr at 25 °C), provides a viable single source precursor for the growth of stoichiometric SiC without the need for post-deposition thermal treatment.

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Development, characterisation and simulation of wafer bonded Si-on-SiC substrates

Cited by 13 publications

References 13 publications

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

Defect- and H-Free Stoichiometric Silicon Carbide by Thermal CVD from the Single Source Precursor Trisilacyclohexane

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