Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

Abstract

A novel Si/SiC heterojunction Lateral Doublediffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The RON,SP of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ•cm 2 of Cov. LDMOS to 24.0mΩ•cm 2 , decreased by 27.7%. Furthermore, the figure-of-merit (FOM=BV 2 /Ron,sp) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm 2 , which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

Real-Life Mission Profile-Oriented Lifetime Estimation of a SiC Interleaved Bidirectional HV DC/DC Converter for Electric Vehicle Drivetrains

“…Detailed electrothermal modelling techniques for power semiconductor devices can be categorized into five types based on literature: (a) behavioural model [26], [46], [47], (b) physical model [48], [49], (c) semi-physical model (i.e., PSpice or SaberRD/ SaberEXP) [50]- [52], (d) numerical model (i.e., numerical tools such as ISE TCAD and MEDICI) [53], [54] and (e) semi-numerical model [55]. The physical models are represented by the composition of the internal layers of the semiconductors [48], [49].…”

“…Hence, the simulation speed is slow because the switching behavior needs to be simulated in detail. The numerical models in [53], [54] also have a high computation time due to the required settings of material performance and the geometry size of the devices. Furthermore, the semi-numerical models in [55] are based on geometrical microstructure parameters and composite elastic properties that are obtained using finite element analysis (FEA); hence, this type of model is not a potential candidate for .…”

A SiC asymmetric cell trench MOSFET with a split gate and integrated p+-poly Si/SiC heterojunction freewheeling diode

“…Some researchers embed heterojunction diodes in power devices to improve the electrical performance of the devices. [24][25][26][27][28][29] Yu et al [24] reported a novel SiC power MOS-FET structure. Yoon [25] proposed a SiC MOSFET insted heterojunction diode, which provided some protection against the electric field.…”

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

“…In the present study, Silvaco T-CAD Atlas software 5.34.0.R [8][9][10][11] was used to perform n-LDMOS modulation simulations. The plate effect [12][13][14][15][16][17] was employed to arrange a floating poly [17][18][19] on the oxide layer (STI). The design was intended to take advantage of the field-saka effect to increase the breakdown voltage (VBK) while reducing the maximum electric field.…”