Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

IEEE J. Electron Devices Soc.

Yang

et al. 2020

Self Cite

In this paper, a new vertical double-diffused metal-oxide semiconductor field effect transistors (VDMOS) is proposed with the partial SiC/Si heterojunction (Partial SiC/Si VDMOS) under the drain electrode in this paper for the first time. The breakdown point transfer technique (BPT) is used to transfer the breakdown point from the radius of curvature is large to the radius of curvature is small in the interface between Pwell and Ndrift region, which causes the longitudinal peak value of electric field to be raised, and the higher breakdown voltage (BV) can be obtained. At the same time, the formation of highly doped Ntype silicon trench alleviates interface state problems caused by current flowing through SiC/Si heterojunction and further optimized the whole SiC/Si heterojunction (SiC/Si VDMOS). The limit line of the silicon has been broken because the result is improved between the BV and the specific on-resistance (R on,sp). Compared with the conventional Si VDMOS, the BV is increased from 238V to 342V, and the R on,sp is reduced from 14.24m •cm 2 to 13.92m •cm 2. INDEX TERMS VDMOS, partial SiC/Si heterojunction, breakdown point transfer technique, interface state.

Section: Resultsmentioning

confidence: 93%

Novel Power MOSFET With Partial SiC/Si Heterojunction to Improve Breakdown Voltage by Breakdown Point Transfer (BPT) Terminal Technology

Wang

IEEE J. Electron Devices Soc.

Yang

et al. 2020

Self Cite

“…It can also be seen from Fig. 10 (a) that the increase of Tepi can be regard as the decrease of TD, which means that the proposed structure can achieve a better performance with a thinner epitaxial layer [20].…”

Section: Regionmentioning

confidence: 82%

“…Therefore, based on those points, a Si/SiC heterojunction LDMOS with the SIPOS field plate (SIPOS Si/SiC LDMOS) is proposed for the first time. This novel device has the following advantages: Firstly, the peak of the electric field is transferred from the surface of drain region to the SiC substrate by the terminal technology of Breakdown Point Transfer (BPT) [18][19][20][21], which can improve the BV compared with Cov. LDMOS.…”

Section: Introductionmentioning

confidence: 99%

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

IEEE J. Electron Devices Soc.

Xue

Huang

et al. 2021

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A novel Si/SiC heterojunction Lateral Doublediffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The RON,SP of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ•cm 2 of Cov. LDMOS to 24.0mΩ•cm 2 , decreased by 27.7%. Furthermore, the figure-of-merit (FOM=BV 2 /Ron,sp) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm 2 , which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

“…[21] Ref. [25] Partial GaN/Si UMOS Silicon limit line The R on,sp versus BV in MOSFET with different structures are compared in figure 12 [18][19][20][21][22][23][24][25]. The BV and the R on,sp of partial GaN/Si VDMOS are 325 V and 10.17 mΩ cm 2 , and partial GaN/Si UMOS are 279 V and 2.34 mΩ cm 2 .…”

Section: Resultsmentioning

confidence: 99%

Novel vertical power MOSFET with partial GaN/Si heterojunction to improve breakdown voltage by breakdown point transfer terminal technology

Wang

Semicond. Sci. Technol.

Yang

et al. 2020

Self Cite

In this paper, the vertical power MOSFET with partial GaN/Si heterojunction is proposed, and the partial GaN/Si heterojunction double-diffused MOSFET (partial GaN/Si VDMOS) and U-shaped MOSFET (partial GaN/Si UMOS) are simulated. Thanks to the breakdown point transfer technology, the breakdown point is transferred from the high electric field area to the low electric field area, therefore, the breakdown voltage (BV) is improved. Different types of dangling bonds are introduced to simulate the influence of different interface state densities on the forward characteristics of the device, the proposed structure alleviates the influence of interface state occurring in the whole GaN/Si heterojunction VDMOS and UMOS (GaN/Si VDMOS and GaN/Si UMOS). The results show that the BV and the specific on-resistance of partial GaN/Si VDMOS are 325 V and 10.17 mΩ cm2, and of partial GaN/Si UMOS are 279 V and 2.34 mΩ cm2, all of which break the limit relation of silicon.