Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node

Rezgui, Houssem; Nasri, Faouzi; Nastasi, Giovanni; Aissa, Mohamed Fadhel Ben; Rahmouni, Salah; Romano, Vittorio; Belmabrouk, Hafedh; Guizani, Amenallah

doi:10.1088/1361-6463/abaf7c

Cited by 13 publications

(4 citation statements)

References 35 publications

(67 reference statements)

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“…To understand this behavior, we performed finite element method (FEM) based COMSOL Multiphysics simulation of the VNWFETs under the same pulsed conditions as the measurements. The simulation method relies on the partial differential equation (PDE) package in COMSOL for transport equations coupling phonon and electron transport by solving the non-Fourier heat equation and a drift-diffusion model with interface trapping effects [6]. In addition, simulations with the VNWFET compact model [7] have also been performed and the two simulations are compared with the experimental results in Fig.…”

Section: Resultsmentioning

confidence: 99%

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Wang,

Mukherjee,

Rezgui

et al. 2024

Solid-State Electronics

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Section: Resultsmentioning

confidence: 99%

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Wang,

Mukherjee,

Rezgui

et al. 2024

Solid-State Electronics

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“…To match the transfer characteristics metal gate work function, source/drain lumped series resistance, and for the linear regime, low-field ballistic mobility parameter and saturation regime saturation velocity (v sat ) and high-field saturation parameters are tuned in appropriate limits. Generally, in the nanoscale regime, the phonon mean free path is restricted by the phonon-boundary scattering responsible for reducing the thermal conductivity of the nonplanar nanoscale devices [31,32]. The thermal conductivity (k) of Si-based nanoscale devices is temperature and thickness dependent [33].…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

Rathore¹,

Jaisawal²,

Suryavanshi³

et al. 2022

Semicond. Sci. Technol.

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Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (TD), that ultimately affects the key electrical characteristics, i.e., threshold voltage (VT), DIBL, subthreshold slope (SS), IOFF, ION, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulations. The weak electron-phonon coupling, phonon scattering, and the ambient temperature-induced joule energy directly coupled with thermal contact resistance cause the SHE-induced thermal degradation, which increases the device temperature (TD) and affects the device reliability. The baseline NS-FET is well-calibrated with the experimental data and 3D quantum corrected drift-diffusion coupled hydrodynamic and thermodynamic transport models is used in our TCAD framework to estimate the impact of ambient temperature and interface thermal contact resistance on the device performance. Moreover, we also evaluate the SHE-induced performance comparison of NS-FET with conventional FinFET and found that thermal degradation in NS-FET potentially worsen the electrical characteristics. Thus, a detailed TCAD analysis shows that the ambient temperature and interface thermal contact resistances deteriorate the effective thermal resistance (Reff) and device performance metrics.

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“…However, SOI devices also suffer from inherent self-heating effects (SHEs), leading to adverse effects such as saturation drive current degradation and transconductance distortion [4,5]. This thermal issue will be further exacerbated by the development of SOI technology combined with advanced devices and the integration of 3D devices, necessitating urgent research on SHEs [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer

Li,

Xu,

et al. 2024

J. Phys. D: Appl. Phys.

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Silicon-on-insulator (SOI) devices are widely utilized in high-performance and high-reliability fields, facing challenges from self-heating effects (SHE). However, the research on heat dissipation path closely related to SHE remains incomplete. This paper initiates an in-depth analysis of thermal effects involving the fine structures within heat dissipation path, using ultrafast pulse I-V measurements combined with thermal simulations. It is found in practical processes that the SHE of scaled-down devices decreased by 40% rather than increase. Research shows the improvement is attributed to the reduction in thickness of buried oxide (BOX) layer between different generations of processes, and the decrease in thermal sensitivity. Based on the two-stage SHE mechanism, the study clarified for the first time that the box layer mainly affects first-stage heat dissipation, and the main timescale of impact is about the first 100ns. In addition, the heat dissipation capability of contact can effectively affect the temperature rise of first-stage SHE. For the first time, we reveal that the TiN barrier layer with low thermal conductivity is the key factor limiting heat dissipation through contact. This study represents the crucial step towards a comprehensive investigation of SHE, offering substantial support for device modeling.

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Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node

Cited by 13 publications

References 35 publications

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer

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