Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Wang, Y.; Mukherjee, C.; Rezgui, H.; Deng, M.; Müller, J.; Pelloquin, S.; Larrieu, G.; Maneux, C.

doi:10.1016/j.sse.2023.108805

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Cited by 3 publications

References 15 publications

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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

Wang,

Mukherjee,

Rezgui

et al. 2023

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)

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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

Wang,

Mukherjee,

Rezgui

et al. 2023

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)

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3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

Mannaa,

Poittevin,

Marchand

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heattransport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit level simulations indicate a strong impact of temperature variation on functionality and figures of merits such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

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Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods

Mukherjee,

Rezgui,

Wang

et al. 2023

IEEE Trans. Electron Devices

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In this paper, we present the first detailed experimental study of electro-thermal effects in 3D vertical gate-all-around junctionless nanowire transistors (JLNT). In contrast with conventional CMOS technologies, JLNTs exhibit steady increase of current with temperature owing to weak mobility degradation in the highly doped nanowires. Consequently, in this work, we proposed novel experimental methods for extracting thermal resistance using DC and low-frequency S-parameter measurements. Experimental results obtained from different methods are validated against theoretical as well as simulated values obtained from multiphysics simulation of JLNTs.

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Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Cited by 3 publications

References 15 publications

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs

Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods

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