Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS

McIntyre, H.; Arekapudi, S.; Busta, Eric; Fischer, Tim; Golden, M.; Horiuchi, Aaron; Meneghini, T.; Naffziger, Samuel; Vinh, James

doi:10.1109/jssc.2011.2167823

Cited by 22 publications

(15 citation statements)

References 6 publications

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“…1 composes the 8-read + 4-write register file of a replicated pair of 4-read + 4-write RAMs to reduce the ports from 12 to 8 though the number of cells are doubled. Such replication is widely used for recent processors [3], [12], [15]- [18].…”

Section: Reducing Register File Portsmentioning

confidence: 99%

“…This replication is widely used in recent cores such as the Bulldozer core in Sect. 1 [3], [12], [15]- [18]. Table 3 gives its configuration, which follows modern 8-issue cores such as the IBM POWER7/8, and Intel Haswell and Skylake processors [3]- [6].…”

Section: Baseline Modelmentioning

confidence: 99%

“…Besides, the circuit area of a register file composed of a RAM is proportional to the square of the number of its ports [7]- [9]. Figure 1 shows a die photograph of the AMD Bulldozer processor, which is the most documented in recent processors [10]- [12]. The integer core of the processor is a moderate-sized, non-multithreaded 4-issue one.…”

Section: Introductionmentioning

confidence: 99%

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Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.

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Section: Reducing Register File Portsmentioning

confidence: 99%

Section: Baseline Modelmentioning

confidence: 99%

See 1 more Smart Citation

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…Multicore processors are ubiquitous in desktops, servers, and embedded devices [1,18,20]. Computer architects designed multicore processors to overcome the limitations of superscalar processors (e.g., poor performance per Watt ratios) whose performance stopped growing at historical rate.…”

Section: Introductionmentioning

confidence: 99%

A performance-aware quality of service-driven scheduler for multicore processors

2014

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In the latest decade, the IT industry shifted from single to multicore processors. Multicore processors require better support from operating systems and runtimes to allow applications to achieve predictable performance and guarantee quality of service (QoS). Finding a proper schedule to yield the specified performance for single and multi-threaded applications can be cumbersome; dealing with multi-programmed workloads may be even worse.We present a performance-aware QoS-driven scheduler for multicore processors, which exploits the availability of runtime application-specific performance measurements to determine a suitable allotment of cores for multi-programmed workloads so as to achieve the desired level of QoS. The proposed scheduler is meant to be implemented in user-mode and harnesses an auto-regressive moving average performance model to put in a relationship performance measurements and resource allocation and is capable of embodying applications' characteristics such as execution phases.

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“…Clock energy dissipation continues to play a significant role in determining the energy-efficiency of a wide range of digital systems, from high performance microprocessors [8][9][10]13] to ultralow power digital circuits employing aggressive pipelining [7]. Following several prototype demonstrations [1-3, 6, 14-16, 18], resonant clocking has emerged as a promising technique to reduce the substantial power dissipated in commercial processor clock distributions [5,10,13].…”

Section: Introductionmentioning

confidence: 99%

Quasi-resonant clocking

Sathe

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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Resonant clocking has emerged as a promising approach for achieving energy-efficiency in high-performance digital systems. However, the limited frequency range of efficient resonant clocking operation restricts its applicability in widely-used Dynamic Voltage and Frequency Scaling (DVFS) systems. Existing frequency-scalable resonant clocking implementations are either not voltage-scalable, or provide only modest frequency range extension. This paper presents a true voltage and frequency-scalable quasi-resonant clock architecture. Simulations on a 64-bit pipelined multiply-accumulate unit in 65nm CMOS demonstrate continuous frequency scalability over 2-200MHz. Efficient operation during dynamic voltage frequency-scaling is demonstrated over 0.8V-1.3V, resulting in a 54% energy-per cycle reduction over conventional distributions.

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Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS

Cited by 22 publications

References 6 publications

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

A performance-aware quality of service-driven scheduler for multicore processors

Quasi-resonant clocking

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