We previously reported that a low-protein diet caused animals to develop fatty liver containing a high level of triglycerides (TG), similar to the human nutritional disorder “kwashiorkor”. To investigate the underlying mechanisms, we cultured hepatocytes in amino acid-sufficient or deficient medium. Surprisingly, the intracellular TG level was increased by amino acid deficiency without addition of any lipids or hormones, accompanied by enhanced lipid synthesis, indicating that hepatocytes themselves monitored the extracellular amino acid concentrations to induce lipid accumulation in a cell-autonomous manner. We then confirmed that a low-amino acid diet also resulted in the development of fatty liver, and supplementation of the low-amino acid diet with glutamic acid to compensate the loss of nitrogen source did not completely suppress the hepatic TG accumulation. Only a dietary arginine or threonine deficiency was sufficient to induce hepatic TG accumulation. However, supplementation of a low-amino acid diet with arginine or threonine failed to reverse it. In silico analysis succeeded in predicting liver TG level from the serum amino acid profile. Based on these results, we conclude that dietary amino acid composition dynamically affects the serum amino acid profile, which is sensed by hepatocytes and lipid synthesis was activated cell-autonomously, leading to hepatic steatosis.
A register cache has been proposed to solve the problems of the huge register files of recent superscalar processors. The register cache reduces the effective access latency of the register file for IPC improvement, simplifies the bypass network, and reduces the ports of the main register file. Though the primary purpose of the previous works is to improve IPC, the misses on the register cache may degrade the IPC. We propose Non-Latency-Oriented Register Cache System (NORCS). Though the effects of NORCS are the same as the conventional systems, it is free from register cache miss penalties that the conventional systems suffer from. In NORCS, the register cache itself is not different from that of the conventional systems. The difference is that the instruction pipeline has stages to read the main register file, which all instructions go through regardless of register cache hit / miss. Therefore, the instruction pipeline of NORCS is not immediately disturbed by the register cache misses. For a realistic 4-way superscalar processor, NORCS can simplify the bypass network to the same complexity as a 1-cycle-latency register file, and reduce the ports of the main register file from 12 to 4. CACTI simulation shows that the area and power consumption are reduced to 24.9% and 31.9% compared to the baseline model without register cache. Though these results are not different from the conventional systems, IPCs differ greatly. IPC of the conventional system decreases to 83.1% because of the cache miss penalties, while that of NORCS is retained at 98.0%.
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