Quasi-resonant clocking

Abstract

Resonant clocking has emerged as a promising approach for achieving energy-efficiency in high-performance digital systems. However, the limited frequency range of efficient resonant clocking operation restricts its applicability in widely-used Dynamic Voltage and Frequency Scaling (DVFS) systems. Existing frequency-scalable resonant clocking implementations are either not voltage-scalable, or provide only modest frequency range extension. This paper presents a true voltage and frequency-scalable quasi-resonant clock architecture. Simulations on a 64-bit pipelined multiply-accumulate unit in 65nm CMOS demonstrate continuous frequency scalability over 2-200MHz. Efficient operation during dynamic voltage frequency-scaling is demonstrated over 0.8V-1.3V, resulting in a 54% energy-per cycle reduction over conventional distributions.

Design Automation of Series Resonance Clocking in 14-nm FinFETs

“…The skew reduction methodology, described in Chapter 5, explains the inductor Fig. 2 Energy recycling techniques include (a) Quasi-adiabatic clocking topology places a capacitor in parallel with clock load to store energy [13] (b) Parallel resonance topology places an inductor in parallel with clock load [40] (c) Series resonance topology places an inductor in the discharge path of clock load [2] (d) Quasi-resonant clocking topology places an inductor and an additional transistor to conditionally disconnect the inductor [42].…”

“…2 (b)), series resonance [2,4] (Fig. 2 (c)) intermittent resonance [15], and quasi-resonance [42] (Fig. 2 (d)).…”

“…Several low power techniques such as dynamic voltage and frequency scaling (DVFS) [36], clock gating [47], quasi-adiabatic clocking [13] and LC resonant clocking [1,2,7,15,24,40,42] are commonly used to address high power consumption in clock networks. In a traditional clocking method, half of the switching power is utilized to charge a capacitive node when the clock transitions from 0-to-1.…”