Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

This letter presents a high-linearity single-pole five-throw switch implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process. In order to improve the linearity of switch, the uniform voltage division across the stacked-FETs is obtained by the proposed structure, which employs a resistive biasing network as well as compensation technology of drain-to-source capacitance and DC balance resistor. The measured input 0.1 dB compression point of the proposed switch is 42 dBm. Insertion losses are 0.38 dB and 0.5 dB for TX and RX modes at 0.9 GHz. The switch exhibits a second harmonic of -91 dBc, and third harmonic power of -84 dBc with a +28 dBm input power at 0.9 GHz.

Section: Introductionmentioning

confidence: 99%

A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

Zhang,

Ma,

et al. 2024

“…With the high frequency and wide bandwidth nature, several millimeter-wave (mm-Wave) bands, such as 28, 39 and 60 GHz, can be used for high data rate 5G communication, high resolution radar sensing and imaging applications [1,2,3,4]. Considering the high propagation loss and line-of-sight (LoS) features of the mm-Wave band, the phase array techniques are employed [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

Effects of underfill on wideband flip-chip packaging for 5G millimeter-wave applications

Xia

Zhang

Liu

et al. 2023

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-toback flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

“…Radar sensors have huge potential in many short-and medium-range applications, where sensors require low cost, low power, small size, and provide reliable performance in various environmental [2,3,4,5,6,7,8,9]. The mm-wave frequency has a large enough bandwidth, which is more advantageous for imaging and MIMO systems [10]. In addition to the cost advantage of CMOS and BiCMOS processes, an inherent advantage of the AOC is that the antenna can be directly connected to the amplifier [11].…”

Section: Introductionmentioning

confidence: 99%

Miniaturized broadband monopole antenna in 130nm CMOS with gain improvement

Huang

Sun

et al. 2022

This paper presents a miniaturized broadband monopole AOC (antenna on chip) for W-band. The AOC miniaturization is achieved by a hexagonal grid at the top layer M6 and a capacitive AMC (artificial magnetic conductor) at the bottom layer M1 based on a 130 nm CMOS process. First, the reflection phase of different modes is analyzed using electromagnetics simulation. Secondly, the axial size of the AOC with AMC is further reduced by 16.2% (compared to a straight monopole antenna with AMC) by using a hexagonal grid, and the impedance is optimized by analyzing the grid angle. The proposed miniaturized monopole antenna has the size of 367 um×194.2 um (0.1 λ 0 × 0.052 λ 0 ) at 81 GHz. Measurements show that the antenna has an impedance bandwidth of 31.5% (75-103 GHz) and a peak gain of −0.35dBi at 85 GHz. The proposed antenna has the smallest reported size and can be applied to W-band FMCW radar system on chip.