A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

Abstract

This letter presents a high-linearity single-pole five-throw switch implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process. In order to improve the linearity of switch, the uniform voltage division across the stacked-FETs is obtained by the proposed structure, which employs a resistive biasing network as well as compensation technology of drain-to-source capacitance and DC balance resistor. The measured input 0.1 dB compression point of the proposed switch is 42 dBm. Insertion losses are 0.38 dB and 0.5 dB for TX and RX modes at 0.9 GHz. The switch exhibits a second harmonic of -91 dBc, and third harmonic power of -84 dBc with a +28 dBm input power at 0.9 GHz.